Abstract
Embedded flash memory plays an increasingly important role for system-on-chip (SOC), especially for battery-powered devices. Testing and diagnosis of embedded flash memory is becoming one of the key development and production issues for many SOC products. Moreover, high density, high capacity, and the integration of heterogeneous cores in an SOC results in long test time, which in turn lead to high test cost. In this paper we propose a new diagonal test algorithm for flash memory that effectively reduces the test time without sacrificing the fault coverage. Both disturb faults and conventional RAM faults are covered. A diagnostic algorithm is also presented, which can distinguish among all the disturb faults and most of the conventional RAM faults. Finally, a built-in self-diagnosis (BISD) scheme is proposed. The BISD circuit implements our algorithms and user-defined ones, and its area overhead is low, e.g., it contains only about 2.551 gates (2-3%) for a 2Mb flash memory. The test time by our diagonal test is reduced by about 42.69% as compared with the best March-like algorithm reported so far.
| Original language | English |
|---|---|
| Pages (from-to) | 37-46 |
| Number of pages | 10 |
| Journal | IEEE International Test Conference (TC) |
| Publication status | Published - 2002 Jan 1 |
| Event | Proceedings International Test Conference - Baltimore, MD, United States Duration: 2002 Oct 7 → 2002 Oct 10 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Applied Mathematics
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Diagonal test and diagnostic schemes for flash memories. / Chiu, Sau Kwo; Yeh, Jen Chieh; Huang, Chih Tsun; Wu, Cheng Wen.
In: IEEE International Test Conference (TC), 01.01.2002, p. 37-46.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - Diagonal test and diagnostic schemes for flash memories
AU - Chiu, Sau Kwo
AU - Yeh, Jen Chieh
AU - Huang, Chih Tsun
AU - Wu, Cheng Wen
PY - 2002/1/1
Y1 - 2002/1/1
N2 - Embedded flash memory plays an increasingly important role for system-on-chip (SOC), especially for battery-powered devices. Testing and diagnosis of embedded flash memory is becoming one of the key development and production issues for many SOC products. Moreover, high density, high capacity, and the integration of heterogeneous cores in an SOC results in long test time, which in turn lead to high test cost. In this paper we propose a new diagonal test algorithm for flash memory that effectively reduces the test time without sacrificing the fault coverage. Both disturb faults and conventional RAM faults are covered. A diagnostic algorithm is also presented, which can distinguish among all the disturb faults and most of the conventional RAM faults. Finally, a built-in self-diagnosis (BISD) scheme is proposed. The BISD circuit implements our algorithms and user-defined ones, and its area overhead is low, e.g., it contains only about 2.551 gates (2-3%) for a 2Mb flash memory. The test time by our diagonal test is reduced by about 42.69% as compared with the best March-like algorithm reported so far.
AB - Embedded flash memory plays an increasingly important role for system-on-chip (SOC), especially for battery-powered devices. Testing and diagnosis of embedded flash memory is becoming one of the key development and production issues for many SOC products. Moreover, high density, high capacity, and the integration of heterogeneous cores in an SOC results in long test time, which in turn lead to high test cost. In this paper we propose a new diagonal test algorithm for flash memory that effectively reduces the test time without sacrificing the fault coverage. Both disturb faults and conventional RAM faults are covered. A diagnostic algorithm is also presented, which can distinguish among all the disturb faults and most of the conventional RAM faults. Finally, a built-in self-diagnosis (BISD) scheme is proposed. The BISD circuit implements our algorithms and user-defined ones, and its area overhead is low, e.g., it contains only about 2.551 gates (2-3%) for a 2Mb flash memory. The test time by our diagonal test is reduced by about 42.69% as compared with the best March-like algorithm reported so far.
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M3 - Conference article
AN - SCOPUS:0036446395
SP - 37
EP - 46
JO - IEEE International Test Conference (TC)
JF - IEEE International Test Conference (TC)
SN - 1089-3539
ER -