TY - GEN
T1 - Digital Low-Dropout Regulator Design Methodology for Performance Assessment in Early Stages of Integrated Circuit Design
AU - Chen, Wei Jen
AU - Huang, Chung Hsun
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - This paper presents a generalized digital low-dropout regulator (DLDO) modeling technique that can be adapted to various commonly seen DLDO architectures. With such a technique,a DLDO design methodology is developed to enable performance assessment in the early stages of integrated circuit design,thereby reducing the time required to make late-stage design changes,which would otherwise be extremely time-consuming. Using an actual DLDO design as a test case,experimental results show that the performance predicted by the proposed model is highly consistent with the post-layout simulations.
AB - This paper presents a generalized digital low-dropout regulator (DLDO) modeling technique that can be adapted to various commonly seen DLDO architectures. With such a technique,a DLDO design methodology is developed to enable performance assessment in the early stages of integrated circuit design,thereby reducing the time required to make late-stage design changes,which would otherwise be extremely time-consuming. Using an actual DLDO design as a test case,experimental results show that the performance predicted by the proposed model is highly consistent with the post-layout simulations.
UR - http://www.scopus.com/inward/record.url?scp=85124900421&partnerID=8YFLogxK
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U2 - 10.1109/IFEEC53238.2021.9661996
DO - 10.1109/IFEEC53238.2021.9661996
M3 - Conference contribution
AN - SCOPUS:85124900421
T3 - 2021 IEEE International Future Energy Electronics Conference, IFEEC 2021
BT - 2021 IEEE International Future Energy Electronics Conference, IFEEC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2021 IEEE International Future Energy Electronics Conference, IFEEC 2021
Y2 - 16 November 2021 through 19 November 2021
ER -