Digital offset trimming techniques for CMOS MEMS accelerometers

Po Chang Wu, Bin Da Liu, Sheng Hsiang Tseng, Hann Huei Tsai, Ying Zong Juang

Research output: Contribution to journalArticle

18 Citations (Scopus)

Abstract

This paper presents a digital trimming technique for canceling the output offsets caused by sensor mismatches in an accelerometer design. The offset cancellation techniques provide fine trimming steps with higher chip area efficiency compared with that of conventional capacitor array compensation approaches. The accelerometer, fabricated in a 0.18-μm complementary metal-oxide-semiconductor micro-electro-mechanical-system process, containing the micro-mechanical structure and readout circuits, occupies only a 0.64 × 0.9 mm2 area. The chip draws 0.4 mA from a 1.8-V supply. The measured sensitivity is 195 mV/g and the nonlinearity is 0.78% within the ± 12 g sensing range. The output noise floor is 150 μ/√Hz, corresponding to a 1-g 100-Hz sinusoidal acceleration. The output offset voltage can be trimmed from several tens to several hundreds of millivolts down to several millivolts.

Original languageEnglish
Article number6617702
Pages (from-to)570-577
Number of pages8
JournalIEEE Sensors Journal
Volume14
Issue number2
DOIs
Publication statusPublished - 2014 Feb

All Science Journal Classification (ASJC) codes

  • Instrumentation
  • Electrical and Electronic Engineering

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    Wu, P. C., Liu, B. D., Tseng, S. H., Tsai, H. H., & Juang, Y. Z. (2014). Digital offset trimming techniques for CMOS MEMS accelerometers. IEEE Sensors Journal, 14(2), 570-577. [6617702]. https://doi.org/10.1109/JSEN.2013.2284284