Double-gate CMOS evaluation for 45nm technology node

Meng-Hsueh Chiang, Judy X. An, Zoran Krivokapic, Bin Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Performance of Double-Gate (DG) CMOS is evaluated via device and SPICE circuit simulation using a physical compact model and a look-up table (LUT) model approach. In this work, LUT models are generated for the first time for DG MOSFETs at ITRS 45nm technology node. A physical compact model is further used for device scaling and sensitivity study. It is essential to project what benefits DG device can offer, and, on the other hand, to assess the pragmatic design issue in circuit implementation when parasitic has to be included. We facilitate SPICE simulation to address the DG device performance advantages over conventional single-gate (SG) device at ITRS 45nm technology node. We also discuss whether and how much the DG benefits will be undermined by parasitic.

Original languageEnglish
Title of host publication2003 Nanotechnology Conference and Trade Show - Nanotech 2003
EditorsM. Laudon, B. Romanowicz
Pages326-329
Number of pages4
Volume2
Publication statusPublished - 2003
Event2003 Nanotechnology Conference and Trade Show - Nanotech 2003 - San Francisco, CA, United States
Duration: 2003 Feb 232003 Feb 27

Other

Other2003 Nanotechnology Conference and Trade Show - Nanotech 2003
CountryUnited States
CitySan Francisco, CA
Period03-02-2303-02-27

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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