Double-gate CMOS evaluation for 45nm technology node

Performance of Double-Gate (DG) CMOS is evaluated via device and SPICE circuit simulation using a physical compact model and a look-up table (LUT) model approach. In this work, LUT models are generated for the first time for DG MOSFETs at ITRS 45nm technology node. A physical compact model is further used for device scaling and sensitivity study. It is essential to project what benefits DG device can offer, and, on the other hand, to assess the pragmatic design issue in circuit implementation when parasitic has to be included. We facilitate SPICE simulation to address the DG device performance advantages over conventional single-gate (SG) device at ITRS 45nm technology node. We also discuss whether and how much the DG benefits will be undermined by parasitic.