DRAM system simulation speed-Up by effective-cycle selection

Full system simulation is a developing methodology that aids to find the optimized configurations of system design. Huge amount of data is collected to better characterize the performance of the system. This process requires both accuracy and speed. Cycle-accurate modeling is precise but time and resource consuming. Higher abstraction level of modeling, such as transaction-level modeling, trades accuracy for speed. We propose a novel approach called 'Effective-cycle Selection' to reduce redundant check of command scheduler in memory controller without affecting the functionality. Redundant checks occur in the cycles in which no command would be issued by the command scheduler. By predicting effective cycles, the proposed method diminishes redundancy and speed up simulation by up to 40% in multi-program real workloads, while introducing zero error in simulation compared to the cycle-based simulator. To the best of our knowledge, this is the first research work which leverages the redundancy of memory command scheduling to accelerate simulation.