Dual-core virtual platform with QEMU and SystemC

Cheng Shiuan Peng, Li Chuan Chang, Chih Hung Kuo, Bin Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

Dual-core platforms are growing as a new industry trend as platforms with only one core cannot easily perform the diverse functions in current embedded system applications, such as smart phones. We establish an easy-to-use co-simulation dual-core virtual platform to validate the functionality of hardware and software jointly. In our platform, the hardware components are implemented by SystemC, and two ARM CPUs which are emulated by QEMU, executing the software functions. To control the data flow, BSD sockets are employed to deliver data to each component, including shared memory, hardware modules and QEMU. A thread controller is also built to handle the system thread between the different cores. We verify the dual-core virtual platform using an advanced H.264/A VC encoder SystemC model and a H.264/AVC decoder. The model is controlled by a QEMU emulated ARM CPU, and another ARM CPU executes the decoder flow.

Original languageEnglish
Title of host publication2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
Pages69-72
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
Duration: 2010 Nov 182010 Nov 19

Publication series

Name2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other2010 International Symposium on Next-Generation Electronics, ISNE 2010
CountryTaiwan
CityKaohsiung
Period10-11-1810-11-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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