Dual Path Binary Neural Network

Pei Yin Chen, Chi Huan Tang, Wei Ting Chen, Hui Liang Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Binary neural networks can effectively reduce the number of required parameters but might decrease the classification accuracy. To solve the problem, we propose a dual-path binary neural network (DPBNN) in this paper. Experimental results show that our DPBNN can outperform other traditional binary neural network in CIFAR-10 and SVHN dataset. The proposed network is simple, so it is suitable to be implemented on embedded systems or SoC designs.

Original languageEnglish
Title of host publicationProceedings - 2019 International SoC Design Conference, ISOCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages251-252
Number of pages2
ISBN (Electronic)9781728124780
DOIs
Publication statusPublished - 2019 Oct
Event16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of
Duration: 2019 Oct 62019 Oct 9

Publication series

NameProceedings - 2019 International SoC Design Conference, ISOCC 2019

Conference

Conference16th International System-on-Chip Design Conference, ISOCC 2019
CountryKorea, Republic of
CityJeju
Period19-10-0619-10-09

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Electrical and Electronic Engineering
  • Instrumentation
  • Artificial Intelligence
  • Hardware and Architecture

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  • Cite this

    Chen, P. Y., Tang, C. H., Chen, W. T., & Yu, H. L. (2019). Dual Path Binary Neural Network. In Proceedings - 2019 International SoC Design Conference, ISOCC 2019 (pp. 251-252). [9027649] (Proceedings - 2019 International SoC Design Conference, ISOCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC47750.2019.9027649