Dynamic pipeline architecture for adaptive binary arithmetic codes

Jer-Min Jou, Shiann Rong Kuang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a dynamic pipeline hardware architecture for the adaptive division-free binary arithmetic coding algorithm in [7]. To obtain a high throughput pipeline architecture, we analyze and modify the data dependencies in the algorithm which prevent the use of pipelining, and a novel technique called dynamic pipelining is developed to pipeline the execution of the algorithm with variant pipeline latencies. As a result, a significant speed-up relative to the sequential architecture can be achieved. The dynamic pipeline architecture has been implemented and simulated by Verilog HDL using 0.8μm CMOS technology. Under Verilog simulation, the design can yield a compression and decompression rate of 12 Mbits/sec with a clock rate of 50 MHz.

Original languageEnglish
Title of host publication7th International Symposium on IC Technology, Systems and Applications ISIC 97
Pages478-481
Number of pages4
Volume7
Publication statusPublished - 1997
Event7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore
Duration: 1997 Sep 101997 Sep 12

Other

Other7th International Symposium on IC Technology, Systems and Applications ISIC 97
CountrySingapore
CitySingapore
Period97-09-1097-09-12

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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