TY - JOUR
T1 - Easily testable and fault-tolerant FFT butterfly networks
AU - Li, Jin Fu
AU - Lu, Shyue Kung
AU - Hwang, Shih Arn
AU - Wu, Cheng Wen
N1 - Funding Information:
Manuscript received August 1999; revised April 2000. This work was supported in part by the National Science Council, R.O.C., under Contract NSC87-2218-E262-005 and Contract NSC89-2215-E007-001. This paper was recommended by Associate Editor S. Sriram. J.-F. Li, S.-A. Hwang, and C.-W. Wu are with the Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, R.O.C. S.-K. Lu is with the Department of Electronics Engineering, Fu Jen University, Taipei, Taiwan. Publisher Item Identifier S 1057-7130(00)07758-2.
PY - 2000/9/1
Y1 - 2000/9/1
N2 - With the advent of deep submicron very large scale integration technology, the integration of a large fast-Fourier-transform (FFT) network into a single chip is becoming possible. However, a practical FFT chip is normally very big, so effective testing and fault-tolerance techniques usually are required. In this paper, we first propose a C-testable FFT network design. Only 20 test patterns are required to cover all combinational single-cell faults and interconnect stuck-at and break faults for the FFT network, regardless of its size. A spare-row based fault-tolerant FFT network design is subsequently proposed. Compared with previous works, our approach shows higher reliability and lower hardware overhead, and only three bit-level cell types are needed for repairing a faulty row in the multiply-subtract-add module. Also, special cell design is not required to implement the reconfiguration scheme. The hardware overhead for the testable design is low - about 4% for 16-bit numbers, regardless of the FFT network size.
AB - With the advent of deep submicron very large scale integration technology, the integration of a large fast-Fourier-transform (FFT) network into a single chip is becoming possible. However, a practical FFT chip is normally very big, so effective testing and fault-tolerance techniques usually are required. In this paper, we first propose a C-testable FFT network design. Only 20 test patterns are required to cover all combinational single-cell faults and interconnect stuck-at and break faults for the FFT network, regardless of its size. A spare-row based fault-tolerant FFT network design is subsequently proposed. Compared with previous works, our approach shows higher reliability and lower hardware overhead, and only three bit-level cell types are needed for repairing a faulty row in the multiply-subtract-add module. Also, special cell design is not required to implement the reconfiguration scheme. The hardware overhead for the testable design is low - about 4% for 16-bit numbers, regardless of the FFT network size.
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U2 - 10.1109/82.868460
DO - 10.1109/82.868460
M3 - Article
AN - SCOPUS:0034272102
VL - 47
SP - 919
EP - 929
JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
SN - 1057-7130
IS - 9
ER -