TY - JOUR
T1 - Effective hybrid test program development for software-based self-testing of pipeline processor cores
AU - Lu, Tai Hua
AU - Chen, Chung Ho
AU - Lee, Kuen Jong
N1 - Funding Information:
Manuscript received April 03, 2009; revised August 14, 2009. First published December 18, 2009; current version published February 24, 2011. This work was supported in part by the National Science Council, Taiwan under Grant NSC 96-2220-E-006-011 and Grant NSC 97-2221-E-006-250-MY3, and by the Program for Promoting Academic Excellence of Universities in Taiwan.
PY - 2011/3
Y1 - 2011/3
N2 - This paper presents an effective hybrid test program for the software-based self-testing (SBST) of pipeline processor cores. The test program combines a deterministically developed program which explores different levels of processor core information and a block-based random program which consists of a combination of in-order instructions, random-order instructions, return instructions, as well as instruction sequences used to trigger exception/interrupt requests. Due to the complementary nature of this hybrid test program, it can achieve processor fault coverage that is comparable to the performance of the conventional scan chain method. The test response observation methods and their impacts on fault coverage are also investigated. We present the concept of micro observation versus macro observation and show that the most effective method of using SBST is through a multiple input signature register connected to the processor local bus, while conventional methods that observe only the program results in the memory lead to significantly less processor fault coverage.
AB - This paper presents an effective hybrid test program for the software-based self-testing (SBST) of pipeline processor cores. The test program combines a deterministically developed program which explores different levels of processor core information and a block-based random program which consists of a combination of in-order instructions, random-order instructions, return instructions, as well as instruction sequences used to trigger exception/interrupt requests. Due to the complementary nature of this hybrid test program, it can achieve processor fault coverage that is comparable to the performance of the conventional scan chain method. The test response observation methods and their impacts on fault coverage are also investigated. We present the concept of micro observation versus macro observation and show that the most effective method of using SBST is through a multiple input signature register connected to the processor local bus, while conventional methods that observe only the program results in the memory lead to significantly less processor fault coverage.
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U2 - 10.1109/TVLSI.2009.2036184
DO - 10.1109/TVLSI.2009.2036184
M3 - Article
AN - SCOPUS:79952037113
VL - 19
SP - 516
EP - 520
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 3
M1 - 5356222
ER -