Effects of fin width on high-κ/metal gate bulk FinFET devices

Chien Hung Chen; Ying Chien Fang; Sheng Yuan Chu

doi:10.1049/el.2014.1117

Effects of fin width on high-κ/metal gate bulk FinFET devices

Chien Hung Chen, Ying Chien Fang, Sheng Yuan Chu

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

The effects of silicon fin width on the electrostatic characteristics of high-κ/metal gate bulk fin field-effect transistor (FinFET) devices are investigated. Six devices with different layout fin widths and lengths are designed and fabricated. A technology computer-aided design (TCAD) simulation model with the proposed devices simplified as an equivalent circuit with three components (C_ox, C_s and R_s) indicates that for a given layout area, a narrower fin width leads to a worse flat band voltage shift and larger variation of gate capacitance due to increased substrate resistance.

Original language	English
Pages (from-to)	1160-1162
Number of pages	3
Journal	Electronics Letters
Volume	50
Issue number	16
DOIs	https://doi.org/10.1049/el.2014.1117
Publication status	Published - 2014 Jul 31

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el.2014.1117

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abstract = "The effects of silicon fin width on the electrostatic characteristics of high-κ/metal gate bulk fin field-effect transistor (FinFET) devices are investigated. Six devices with different layout fin widths and lengths are designed and fabricated. A technology computer-aided design (TCAD) simulation model with the proposed devices simplified as an equivalent circuit with three components (Cox, Cs and Rs) indicates that for a given layout area, a narrower fin width leads to a worse flat band voltage shift and larger variation of gate capacitance due to increased substrate resistance.",

author = "Chen, {Chien Hung} and Fang, {Ying Chien} and Chu, {Sheng Yuan}",

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N2 - The effects of silicon fin width on the electrostatic characteristics of high-κ/metal gate bulk fin field-effect transistor (FinFET) devices are investigated. Six devices with different layout fin widths and lengths are designed and fabricated. A technology computer-aided design (TCAD) simulation model with the proposed devices simplified as an equivalent circuit with three components (Cox, Cs and Rs) indicates that for a given layout area, a narrower fin width leads to a worse flat band voltage shift and larger variation of gate capacitance due to increased substrate resistance.

AB - The effects of silicon fin width on the electrostatic characteristics of high-κ/metal gate bulk fin field-effect transistor (FinFET) devices are investigated. Six devices with different layout fin widths and lengths are designed and fabricated. A technology computer-aided design (TCAD) simulation model with the proposed devices simplified as an equivalent circuit with three components (Cox, Cs and Rs) indicates that for a given layout area, a narrower fin width leads to a worse flat band voltage shift and larger variation of gate capacitance due to increased substrate resistance.

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