Effects of gate sidewall recess on Al0.2Ga0.8 As/In0.15Ga0.85As PHEMTs by citric-based selective etchant

K. F. Yarn, C. I. Liao, Y. H. Wang, M. P. Houng

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In this report, an effective and simple method of selective gate sidewall recess is proposed to expose the low barrier channel at mesa sidewalls during device isolation for Al0.2Ga0.8 As/In0.15Ga0.85As PHEMTs (pseudomorphic high electron mobility transistors) by using a newly developed citric-acid-based etchant with high selectivity (>250) for GaAs/ Al0.2Ga0.8As or In0.15Ga0.85 As/Al0.2G0.8As interfaces. After sidewall recess, a revealed cavity will exist between the In0.15 Ga0.85As layers and gate metals. Devices with 1 × 100 μm2 exhibit a very low gate leakage current of 2.4 μA/mm even at VGD = -10 V and high gate breakdown voltage over 25 V. As compared to that of no sidewall recess, nearly two orders of reduction in magnitude of gate leakage current and 100% improvement in gate breakdown voltage can be achieved.

Original languageEnglish
Pages (from-to)529-532
Number of pages4
JournalJournal of Materials Science: Materials in Electronics
Volume16
Issue number8
DOIs
Publication statusPublished - 2005 Aug 1

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this