Effects of gate sidewall recess on Al0.2Ga0.8 As/In0.15Ga0.85As PHEMTs by citric-based selective etchant

K. F. Yarn; C. I. Liao; Y. H. Wang; M. P. Houng

doi:10.1007/s10854-005-2728-z

Effects of gate sidewall recess on Al_0.2Ga_0.8 As/In_0.15Ga_0.85As PHEMTs by citric-based selective etchant

K. F. Yarn
, C. I. Liao
, Y. H. Wang
, M. P. Houng

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

In this report, an effective and simple method of selective gate sidewall recess is proposed to expose the low barrier channel at mesa sidewalls during device isolation for Al_0.2Ga_0.8 As/In_0.15Ga_0.85As PHEMTs (pseudomorphic high electron mobility transistors) by using a newly developed citric-acid-based etchant with high selectivity (>250) for GaAs/ Al_0.2Ga_0.8As or In_0.15Ga_0.85 As/Al_0.2G_0.8As interfaces. After sidewall recess, a revealed cavity will exist between the In_0.15 Ga_0.85As layers and gate metals. Devices with 1 × 100 μm² exhibit a very low gate leakage current of 2.4 μA/mm even at V_GD = -10 V and high gate breakdown voltage over 25 V. As compared to that of no sidewall recess, nearly two orders of reduction in magnitude of gate leakage current and 100% improvement in gate breakdown voltage can be achieved.

Original language	English
Pages (from-to)	529-532
Number of pages	4
Journal	Journal of Materials Science: Materials in Electronics
Volume	16
Issue number	8
DOIs	https://doi.org/10.1007/s10854-005-2728-z
Publication status	Published - 2005 Aug

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1007/s10854-005-2728-z

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@article{2afc0578f9ed49a8ad2963d621ec6219,

title = "Effects of gate sidewall recess on Al0.2Ga0.8 As/In0.15Ga0.85As PHEMTs by citric-based selective etchant",

abstract = "In this report, an effective and simple method of selective gate sidewall recess is proposed to expose the low barrier channel at mesa sidewalls during device isolation for Al0.2Ga0.8 As/In0.15Ga0.85As PHEMTs (pseudomorphic high electron mobility transistors) by using a newly developed citric-acid-based etchant with high selectivity (>250) for GaAs/ Al0.2Ga0.8As or In0.15Ga0.85 As/Al0.2G0.8As interfaces. After sidewall recess, a revealed cavity will exist between the In0.15 Ga0.85As layers and gate metals. Devices with 1 × 100 μm2 exhibit a very low gate leakage current of 2.4 μA/mm even at VGD = -10 V and high gate breakdown voltage over 25 V. As compared to that of no sidewall recess, nearly two orders of reduction in magnitude of gate leakage current and 100\% improvement in gate breakdown voltage can be achieved.",

author = "Yarn, \{K. F.\} and Liao, \{C. I.\} and Wang, \{Y. H.\} and Houng, \{M. P.\}",

note = "Funding Information: The authors would like to thank K. K. Wu, M. C. Chure, S. H. Chang and Far East College for their kindly assistance and the support of film growth during this work.",

year = "2005",

month = aug,

doi = "10.1007/s10854-005-2728-z",

language = "English",

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journal = "Journal of Materials Science: Materials in Electronics",

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AU - Yarn, K. F.

AU - Liao, C. I.

AU - Wang, Y. H.

AU - Houng, M. P.

N1 - Funding Information: The authors would like to thank K. K. Wu, M. C. Chure, S. H. Chang and Far East College for their kindly assistance and the support of film growth during this work.

PY - 2005/8

Y1 - 2005/8

N2 - In this report, an effective and simple method of selective gate sidewall recess is proposed to expose the low barrier channel at mesa sidewalls during device isolation for Al0.2Ga0.8 As/In0.15Ga0.85As PHEMTs (pseudomorphic high electron mobility transistors) by using a newly developed citric-acid-based etchant with high selectivity (>250) for GaAs/ Al0.2Ga0.8As or In0.15Ga0.85 As/Al0.2G0.8As interfaces. After sidewall recess, a revealed cavity will exist between the In0.15 Ga0.85As layers and gate metals. Devices with 1 × 100 μm2 exhibit a very low gate leakage current of 2.4 μA/mm even at VGD = -10 V and high gate breakdown voltage over 25 V. As compared to that of no sidewall recess, nearly two orders of reduction in magnitude of gate leakage current and 100% improvement in gate breakdown voltage can be achieved.

AB - In this report, an effective and simple method of selective gate sidewall recess is proposed to expose the low barrier channel at mesa sidewalls during device isolation for Al0.2Ga0.8 As/In0.15Ga0.85As PHEMTs (pseudomorphic high electron mobility transistors) by using a newly developed citric-acid-based etchant with high selectivity (>250) for GaAs/ Al0.2Ga0.8As or In0.15Ga0.85 As/Al0.2G0.8As interfaces. After sidewall recess, a revealed cavity will exist between the In0.15 Ga0.85As layers and gate metals. Devices with 1 × 100 μm2 exhibit a very low gate leakage current of 2.4 μA/mm even at VGD = -10 V and high gate breakdown voltage over 25 V. As compared to that of no sidewall recess, nearly two orders of reduction in magnitude of gate leakage current and 100% improvement in gate breakdown voltage can be achieved.

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U2 - 10.1007/s10854-005-2728-z

DO - 10.1007/s10854-005-2728-z

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SN - 0957-4522

VL - 16

SP - 529

EP - 532

JO - Journal of Materials Science: Materials in Electronics

JF - Journal of Materials Science: Materials in Electronics

IS - 8

ER -

Effects of gate sidewall recess on Al_0.2Ga_0.8 As/In_0.15Ga_0.85As PHEMTs by citric-based selective etchant

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