Effects of postdeposition annealing on a high-k-last/gate-last integration scheme for 20 nm nMOS and pMOS

Ying Tsung Chen, Ssu I. Fu, Chien Ting Lin, Wen Tai Chiang, Shoou Jinn Chang, Mon Sen Lin, Jyh Shyang Jenq

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4 Citations (Scopus)

Abstract

The authors report the use of postdeposition annealing (PDA) to improve the performance of a high-k (HK)-last/gate-last integration scheme involving the use of a chemical oxide interfacial layer (IL). They find that the chemical oxide IL can form Hf-silicate at the HK/IL interface to provide a larger effective k value and a smaller equivalent oxide thickness. They also find that they can achieve a small gate leakage current density (Jg) and minimal flat-band voltage (Vfb) degradation by PDA in O2 atmosphere. Furthermore, they find that Jg and Vfb can be further improved by optimizing the metal gate stack.

Original languageEnglish
Article number020604
JournalJournal of Vacuum Science and Technology B:Nanotechnology and Microelectronics
Volume31
Issue number2
DOIs
Publication statusPublished - 2013 Mar

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Instrumentation
  • Process Chemistry and Technology
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering
  • Materials Chemistry

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