Effects of substrate structure on the warpage of flip chip IC packages

Yong Sen Lee, Pei Yi Lin, Kuo Tsai Wu, Huei Huang Lee, Sheng Jye Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Warpage after the encapsulation process is a big concern for the plastic IC packaging industry. Too large warp age in a p ackage will cause serious problems, including lower package reliability and, difficulty with post encapsulation processes such as reflow, etc. Thus, accurate prediction of warpage after the encap sulation p rocess is desirable and a number of research works have been done in this area. M ost p revious researchers have focused on thermal-induced warpage analyses considering only the effects of differences in the thermal expansion coefficients between constituent materials and have neglected cure-induced shrinkage effects. However, ep o xy molding compound (EMC) is a thermosetting plastic material, and the colloids will cause volumetric shrinkage due to cure reactions after heating. Ignoring cure-induced volume change effects will cause miscalculations in the amount of warpage, so it is necessary to take into account cure-induced shrinkage in analyses. Therefore, volume shrinkage caused by b ot h EM C cure and temperature effects are considered in this paper. A flip chip IC package is a package with a substrate. M ost substrates in a flip chip IC are made of layers of printed wire board materials with different thermal expansion coefficients, such as FR4 or core material, Cu, green paint, and solder mask, etc. Therefore, it is also possible to observe volume shrinkage in a substrate due to cure and thermal effects. However, to simplify the problem, the degree of cure of the substrate is assumed to be fully cured during packaging, so cure-induced shrinkage of substrates is ignored in this paper. Only volume changes due to temperature effects are considered for the substrate. The an aly sis started with a mold f illin g simulation, and using the data for the package temperature and pressure, warp age simulat ions were execut ed. EMC properties were obtained using various standard test techniques. The Cross Castro-Macosko viscosity model was used in this paper. Kamal's cure kinetic model was also used, which was measured with a differential scanning calorimeter (DSC). Cure-induced volume changes were e xp r es sed w it h the P-V-T-C equation, which describes the relationship between changes in the cure-induced volume, degree of cure, pressure, and temperature. Determination of the coefficients in the P-V-T-C equation were done by combining the data from a P-V-T-C test machine and the cure kinetic model. Using the actual en gin eering ap p lications to verify the feasibility of the analytical method, it was found that for a flip chip package, warpage analysis considering both cure and thermal-induced shrinkage is more accurate than that considering thermal expansion only. The results also showed that both the EM C cure shrinkage and substrate design play a significant role in warpage analyses for flip chip IC packages.

Original languageEnglish
Title of host publication13th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2018
PublisherIEEE Computer Society
Pages66-70
Number of pages5
ISBN (Electronic)9781538656150
DOIs
Publication statusPublished - 2019 Jan 24
Event13th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2018 - Taipei, Taiwan
Duration: 2018 Oct 242018 Oct 26

Publication series

NameProceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT
Volume2018-October
ISSN (Print)2150-5934
ISSN (Electronic)2150-5942

Conference

Conference13th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2018
CountryTaiwan
CityTaipei
Period18-10-2418-10-26

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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