Efficient approach for in-place scheduling of path metric update in Viterbi decoders

Chien Ming Wu, Ming-Der Shieh, Chien Hsing Wu, Ming Hwa Sheu

Research output: Contribution to journalConference articlepeer-review

5 Citations (Scopus)

Abstract

The in-place path metric updating is a well-known technique for efficiently dealing with the management of path metric memory in Viterbi decoders. In this paper, we present a simple but efficient technique to partition the path metric memory into 2i banks and then distribute a set of path metrics into scheduled add_compare_select (ACS) units. Results show that applying the presented scheduling technique the equivalent memory bandwidth can be increased with limited hardware overhead. The resulting architecture has the following characteristics: (1) the interconnection overhead between ACS units and the memory bank structure can be significantly reduced, (2) the control circuit is regular and the implementation can be derived in a systematic way. Therefore, the architecture can be easily applied to handle the convolutional code with a long constraint length and it is suitable to be implemented in VLSI applications.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
Publication statusPublished - 2000 Jan 1
EventProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz
Duration: 2000 May 292000 May 31

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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