Efficient approach for in-place scheduling of path metric update in Viterbi decoders

Chien Ming Wu, Ming-Der Shieh, Chien Hsing Wu, Ming Hwa Sheu

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

The in-place path metric updating is a well-known technique for efficiently dealing with the management of path metric memory in Viterbi decoders. In this paper, we present a simple but efficient technique to partition the path metric memory into 2i banks and then distribute a set of path metrics into scheduled add_compare_select (ACS) units. Results show that applying the presented scheduling technique the equivalent memory bandwidth can be increased with limited hardware overhead. The resulting architecture has the following characteristics: (1) the interconnection overhead between ACS units and the memory bank structure can be significantly reduced, (2) the control circuit is regular and the implementation can be derived in a systematic way. Therefore, the architecture can be easily applied to handle the convolutional code with a long constraint length and it is suitable to be implemented in VLSI applications.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
Publication statusPublished - 2000 Jan 1
EventProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz
Duration: 2000 May 292000 May 31

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Scheduling
Data storage equipment
Convolutional codes
Computer hardware
Bandwidth
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{6bf0895f24db43bea73f1765180bbd4b,
title = "Efficient approach for in-place scheduling of path metric update in Viterbi decoders",
abstract = "The in-place path metric updating is a well-known technique for efficiently dealing with the management of path metric memory in Viterbi decoders. In this paper, we present a simple but efficient technique to partition the path metric memory into 2i banks and then distribute a set of path metrics into scheduled add_compare_select (ACS) units. Results show that applying the presented scheduling technique the equivalent memory bandwidth can be increased with limited hardware overhead. The resulting architecture has the following characteristics: (1) the interconnection overhead between ACS units and the memory bank structure can be significantly reduced, (2) the control circuit is regular and the implementation can be derived in a systematic way. Therefore, the architecture can be easily applied to handle the convolutional code with a long constraint length and it is suitable to be implemented in VLSI applications.",
author = "Wu, {Chien Ming} and Ming-Der Shieh and Wu, {Chien Hsing} and Sheu, {Ming Hwa}",
year = "2000",
month = "1",
day = "1",
language = "English",
volume = "3",
journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
issn = "0271-4310",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

Efficient approach for in-place scheduling of path metric update in Viterbi decoders. / Wu, Chien Ming; Shieh, Ming-Der; Wu, Chien Hsing; Sheu, Ming Hwa.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 3, 01.01.2000.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Efficient approach for in-place scheduling of path metric update in Viterbi decoders

AU - Wu, Chien Ming

AU - Shieh, Ming-Der

AU - Wu, Chien Hsing

AU - Sheu, Ming Hwa

PY - 2000/1/1

Y1 - 2000/1/1

N2 - The in-place path metric updating is a well-known technique for efficiently dealing with the management of path metric memory in Viterbi decoders. In this paper, we present a simple but efficient technique to partition the path metric memory into 2i banks and then distribute a set of path metrics into scheduled add_compare_select (ACS) units. Results show that applying the presented scheduling technique the equivalent memory bandwidth can be increased with limited hardware overhead. The resulting architecture has the following characteristics: (1) the interconnection overhead between ACS units and the memory bank structure can be significantly reduced, (2) the control circuit is regular and the implementation can be derived in a systematic way. Therefore, the architecture can be easily applied to handle the convolutional code with a long constraint length and it is suitable to be implemented in VLSI applications.

AB - The in-place path metric updating is a well-known technique for efficiently dealing with the management of path metric memory in Viterbi decoders. In this paper, we present a simple but efficient technique to partition the path metric memory into 2i banks and then distribute a set of path metrics into scheduled add_compare_select (ACS) units. Results show that applying the presented scheduling technique the equivalent memory bandwidth can be increased with limited hardware overhead. The resulting architecture has the following characteristics: (1) the interconnection overhead between ACS units and the memory bank structure can be significantly reduced, (2) the control circuit is regular and the implementation can be derived in a systematic way. Therefore, the architecture can be easily applied to handle the convolutional code with a long constraint length and it is suitable to be implemented in VLSI applications.

UR - http://www.scopus.com/inward/record.url?scp=0033683088&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033683088&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0033683088

VL - 3

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -