TY - GEN
T1 - Efficient architecture for Reed-Solomon decoder
AU - Lu, Yung Kuei
AU - Shieh, Ming-Der
PY - 2012/7/25
Y1 - 2012/7/25
N2 - An efficient Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (RiBM) algorithm is presented in this paper. Applying the developed control scheme and the simplified boundary cell, the resulting design can significantly reduce the hardware complexity and have a high throughput rate. Compared with the related works, the proposed design has the advantage of area-time complexity. With TSMC 0.18m process, the simulation results reveal that the developed RS(255,239) decoder can operate up to 425MHz and achieve a throughput rate of 3.4Gbps with a total gate count of 12,668.
AB - An efficient Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (RiBM) algorithm is presented in this paper. Applying the developed control scheme and the simplified boundary cell, the resulting design can significantly reduce the hardware complexity and have a high throughput rate. Compared with the related works, the proposed design has the advantage of area-time complexity. With TSMC 0.18m process, the simulation results reveal that the developed RS(255,239) decoder can operate up to 425MHz and achieve a throughput rate of 3.4Gbps with a total gate count of 12,668.
UR - http://www.scopus.com/inward/record.url?scp=84864050635&partnerID=8YFLogxK
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U2 - 10.1109/VLSI-DAT.2012.6212603
DO - 10.1109/VLSI-DAT.2012.6212603
M3 - Conference contribution
AN - SCOPUS:84864050635
SN - 9781457720819
T3 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
BT - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
T2 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
Y2 - 23 April 2012 through 25 April 2012
ER -