Efficient architecture for Reed-Solomon decoder

Yung Kuei Lu, Ming-Der Shieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

An efficient Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (RiBM) algorithm is presented in this paper. Applying the developed control scheme and the simplified boundary cell, the resulting design can significantly reduce the hardware complexity and have a high throughput rate. Compared with the related works, the proposed design has the advantage of area-time complexity. With TSMC 0.18m process, the simulation results reveal that the developed RS(255,239) decoder can operate up to 425MHz and achieve a throughput rate of 3.4Gbps with a total gate count of 12,668.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
Publication statusPublished - 2012 Jul 25
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 2012 Apr 232012 Apr 25

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Other

Other2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan
CityHsinchu
Period12-04-2312-04-25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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