Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation

Harry H. Chen, Simon Y.H. Chen, Po Yao Chuang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)


This paper proposes methods to drastically reduce the expensive analog fault simulation currently used to create cell-aware fault models. By exploiting low-power properties of common CMOS designs, most defects in the transistor-level netlist containing parasitics can be represented by just two canonical fault classes. Via simple circuit analysis, we show that faulty behaviors are completely predictable as the defect resistance parameter value varies from zero to infinity, thus eliminating the need for circuit simulation at multiple parameter values. The two canonical fault classes can be modeled by transistor switch stuck-open and stuck-closed faults. Rather than enumerating the full combination cell input patterns to search for defect detection conditions by analog fault simulation, switch-level test generation can obtain those input conditions directly, thereby reducing significantly the role of analog simulation to that of ranking conditions in terms of detection effectiveness.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)9781509038084
Publication statusPublished - 2016 Dec 22
Event25th IEEE Asian Test Symposium, ATS 2016 - Hiroshima, Japan
Duration: 2016 Nov 212016 Nov 24

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Other25th IEEE Asian Test Symposium, ATS 2016

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


Dive into the research topics of 'Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation'. Together they form a unique fingerprint.

Cite this