Efficient design and generation of a multi-facet arbiter

Jer Min Jou, Yun Lung Lee, Sih Sian Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Based on the arbiter template developed in [1], we presented an efficient, modular, and scalable decentralized parallel design of a new multi-facet arbiter. Moreover, with this modular and reusable hardware design, we have implemented a parametric arbiter generator that automatically generates various multi-facet arbiters. With the decentralized parallel design and the generator, not only a fastest and smallest round-robin arbiter but also other type arbiters were designed and generated on the fly. The experiment results were given to show the designs' excellent performances.

Original languageEnglish
Title of host publicationProceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP'10
Pages111-114
Number of pages4
DOIs
Publication statusPublished - 2010 Aug 24
Event8th IEEE Symposium on Application Specific Processors, SASP'10 - Anaheim, CA, United States
Duration: 2010 Jun 132010 Jun 14

Publication series

NameProceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP'10

Other

Other8th IEEE Symposium on Application Specific Processors, SASP'10
Country/TerritoryUnited States
CityAnaheim, CA
Period10-06-1310-06-14

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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