Efficient diagnostic fault simulation for sequential circuits

Jer Min Jou, Shung Chih Chen

Research output: Contribution to journalConference articlepeer-review


In this paper, an efficient diagnostic fault simulator for sequential circuits is proposed. In it, a two-level optimization technique is developed and used to prompt the processing speed. In the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining algorithm are applied, thus reduces a great deal of diagnostic comparisons among all pairs of faults. In the second low level, a bit-parallel comparison is developed to speed up the comparing process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simulator is extended to diagnose the single stuck-at device fault correctly. Experimental results show that our method achieves a significant speedup compared to previous methods.

Original languageEnglish
Pages (from-to)94-99
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 1994 Dec 1
EventProceedings of the 3rd Asian Test Symposium - Nara, Jpn
Duration: 1994 Nov 151994 Nov 17

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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