Efficient double fault diagnosis for CMOS logic circuits with a specific application to generic bridging faults

Hong Chou Kao, Ming Fu Tsai, Shi Yu Huang, Cheng Wen Wu, Wen Feng Chang, Shyue Kung Lu

Research output: Contribution to journalArticlepeer-review

Abstract

Fault diagnosis that predicts the most likely fault sites in a faulty chip is an important step for manufacturing yield improvement or design debugging. In this paper, we address the problem of double fault diagnosis for full-scan designs. Our algorithm aims to identify both faults accurately. The features of our algorithm include the following. (1) The proposed algorithm is not limited to any particular fault type. (2) An effective selection heuristic is incorporated to significantly reduce the diagnosis time, while retaining a high success rate of catching faults. (3) The inject-and-evaluate paradigm proposed in [6] is incorporated to accurately screen out unlikely fault candidates. Experimental results on ISCAS85 benchmark circuits injected with a generic bridging fault, two stuck-at faults, or two gate-type faults show that both faults can be caught simultaneously within several minutes with a high success rate.

Original languageEnglish
Pages (from-to)571-587
Number of pages17
JournalJournal of Information Science and Engineering
Volume19
Issue number4
Publication statusPublished - 2003 Jul 1

All Science Journal Classification (ASJC) codes

  • Software
  • Human-Computer Interaction
  • Hardware and Architecture
  • Library and Information Sciences
  • Computational Theory and Mathematics

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