Efficient global strategy for designing and testing scanned sequential circuits

B. D. Liu, P. C. Chen, J. F. Wang

Research output: Contribution to journalArticlepeer-review


Previous approaches to scan design have tried individually to enhance the abilities of test generation algorithm and scan cell selection strategy in order to reduce extra costs associated with the time spent on testing. In contrast, a global strategy which takes care of the close relationship between these factors and combines a new scan structure is proposed. Two assertions for the design of test generator are also proposed, and a fault list oriented test generation algorithm is developed in accordance with these two assertions. A simulation-based partial scan methodology is finally introduced for selecting the suitable scanning flip-flops through the utilization of dynamic information generated during fault simulation. Experimental results show that the proposed strategy speeds up test generation and reduces the amount of test application time.

Original languageEnglish
Pages (from-to)170-176
Number of pages7
JournalIEE Proceedings: Computers and Digital Techniques
Issue number2
Publication statusPublished - 1995 Mar 1

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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