Abstract
LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten test-application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a net-selection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 –2.75 % of internal nets and with 2.35 –4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.
| Original language | English |
|---|---|
| Pages (from-to) | 673-685 |
| Number of pages | 13 |
| Journal | Journal of Electronic Testing: Theory and Applications (JETTA) |
| Volume | 30 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 2014 Dec 3 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Efficient LFSR Reseeding Based on Internal-Response Feedback. / Lien, Wei Cheng; Lee, Kuen-Jong; Hsieh, Tong Yu; Chakrabarty, Krishnendu.
In: Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 30, No. 6, 03.12.2014, p. 673-685.Research output: Contribution to journal › Article
TY - JOUR
T1 - Efficient LFSR Reseeding Based on Internal-Response Feedback
AU - Lien, Wei Cheng
AU - Lee, Kuen-Jong
AU - Hsieh, Tong Yu
AU - Chakrabarty, Krishnendu
PY - 2014/12/3
Y1 - 2014/12/3
N2 - LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten test-application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a net-selection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 –2.75 % of internal nets and with 2.35 –4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.
AB - LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten test-application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a net-selection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 –2.75 % of internal nets and with 2.35 –4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.
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U2 - 10.1007/s10836-014-5482-4
DO - 10.1007/s10836-014-5482-4
M3 - Article
AN - SCOPUS:84916242759
VL - 30
SP - 673
EP - 685
JO - Journal of Electronic Testing: Theory and Applications (JETTA)
JF - Journal of Electronic Testing: Theory and Applications (JETTA)
SN - 0923-8174
IS - 6
ER -