TY - JOUR
T1 - Efficient LFSR Reseeding Based on Internal-Response Feedback
AU - Lien, Wei Cheng
AU - Lee, Kuen Jong
AU - Hsieh, Tong Yu
AU - Chakrabarty, Krishnendu
N1 - Funding Information:
Acknowledgments This work is partially supported by Ministry of Science and Technology of Taiwan under contract NSC102-2917-I-006-024, NSC102-2221-E-006-266-MY3, NSC101-2221-E-110-095-MY2 and MOST 103-2221-E-110-077-MY3.
PY - 2014/12/3
Y1 - 2014/12/3
N2 - LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten test-application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a net-selection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 –2.75 % of internal nets and with 2.35 –4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.
AB - LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten test-application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a net-selection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 –2.75 % of internal nets and with 2.35 –4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.
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U2 - 10.1007/s10836-014-5482-4
DO - 10.1007/s10836-014-5482-4
M3 - Article
AN - SCOPUS:84916242759
VL - 30
SP - 673
EP - 685
JO - Journal of Electronic Testing: Theory and Applications (JETTA)
JF - Journal of Electronic Testing: Theory and Applications (JETTA)
SN - 0923-8174
IS - 6
ER -