Efficient LFSR Reseeding Based on Internal-Response Feedback

Wei Cheng Lien, Kuen Jong Lee, Tong Yu Hsieh, Krishnendu Chakrabarty

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)

Abstract

LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten test-application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a net-selection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 –2.75 % of internal nets and with 2.35 –4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.

Original languageEnglish
Pages (from-to)673-685
Number of pages13
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume30
Issue number6
DOIs
Publication statusPublished - 2014 Dec 3

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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