TY - GEN
T1 - Efficient memory management for FFT processors
AU - Luo, Hsin Fu
AU - Shieh, Ming-Der
AU - Liu, Yi Jun
AU - Wu, Chien Ming
PY - 2010/8/31
Y1 - 2010/8/31
N2 - This paper presents an efficient memory management scheme for memory-based architecture of Fast Fourier Transform (FFT). A new data relocating scheme is proposed to merge multiple banks for alleviating the area requirement as well as the power dissipation of memory-based FFT. The proposed memory addressing method can effectively deal with merged-banked single-ported memory with high-radix processing elements. Compared to conventional memory-based FFT designs using two-ported memories, the derived architecture reveals better performance in area requirement and power consumption.
AB - This paper presents an efficient memory management scheme for memory-based architecture of Fast Fourier Transform (FFT). A new data relocating scheme is proposed to merge multiple banks for alleviating the area requirement as well as the power dissipation of memory-based FFT. The proposed memory addressing method can effectively deal with merged-banked single-ported memory with high-radix processing elements. Compared to conventional memory-based FFT designs using two-ported memories, the derived architecture reveals better performance in area requirement and power consumption.
UR - http://www.scopus.com/inward/record.url?scp=77956003557&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77956003557&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2010.5537740
DO - 10.1109/ISCAS.2010.5537740
M3 - Conference contribution
AN - SCOPUS:77956003557
SN - 9781424453085
T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
SP - 3737
EP - 3740
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Y2 - 30 May 2010 through 2 June 2010
ER -