Efficient memory management scheme for pipelined shared-memory FFT processors

Hsin Fu Luo; Ming Der Shieh

doi:10.1109/ICCE-TW.2015.7216842

Efficient memory management scheme for pipelined shared-memory FFT processors

Hsin Fu Luo
, Ming Der Shieh

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents an efficient memory management scheme for pipelined shared-memory architectures of the fast Fourier transform (FFT). A multi-path delay commutator (MDC) with a data relocation scheme is developed to merge multiple banks for lowering the area requirement and power dissipation of pipelined shared-memory FFT architectures. Moreover, a generalized memory addressing algorithm that can support mixed-radix MDC architectures is also proposed. The presented architecture outperforms conventional pipelined shared-memory FFT designs, which employ multi-bank memory structures, in terms of the area requirement and power consumption.

Original language	English
Title of host publication	2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	178-179
Number of pages	2
ISBN (Electronic)	9781479987443
DOIs	https://doi.org/10.1109/ICCE-TW.2015.7216842
Publication status	Published - 2015 Aug 20
Event	2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 - Taipei, Taiwan Duration: 2015 Jun 6 → 2015 Jun 8

Publication series

Name	2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

Other

Other	2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
Country/Territory	Taiwan
City	Taipei
Period	15-06-06 → 15-06-08

All Science Journal Classification (ASJC) codes

Artificial Intelligence
Computer Networks and Communications
Electrical and Electronic Engineering
Instrumentation
Media Technology

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10.1109/ICCE-TW.2015.7216842

Cite this

Luo, H. F., & Shieh, M. D. (2015). Efficient memory management scheme for pipelined shared-memory FFT processors. In 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 (pp. 178-179). Article 7216842 (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE-TW.2015.7216842

@inproceedings{2dd905f0745b4aa7bfff96dbf6853806,

title = "Efficient memory management scheme for pipelined shared-memory FFT processors",

abstract = "This paper presents an efficient memory management scheme for pipelined shared-memory architectures of the fast Fourier transform (FFT). A multi-path delay commutator (MDC) with a data relocation scheme is developed to merge multiple banks for lowering the area requirement and power dissipation of pipelined shared-memory FFT architectures. Moreover, a generalized memory addressing algorithm that can support mixed-radix MDC architectures is also proposed. The presented architecture outperforms conventional pipelined shared-memory FFT designs, which employ multi-bank memory structures, in terms of the area requirement and power consumption.",

author = "Luo, \{Hsin Fu\} and Shieh, \{Ming Der\}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 ; Conference date: 06-06-2015 Through 08-06-2015",

year = "2015",

month = aug,

day = "20",

doi = "10.1109/ICCE-TW.2015.7216842",

language = "English",

series = "2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "178--179",

booktitle = "2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015",

address = "United States",

}

Luo, HF & Shieh, MD 2015, Efficient memory management scheme for pipelined shared-memory FFT processors. in 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015., 7216842, 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015, Institute of Electrical and Electronics Engineers Inc., pp. 178-179, 2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015, Taipei, Taiwan, 15-06-06. https://doi.org/10.1109/ICCE-TW.2015.7216842

Efficient memory management scheme for pipelined shared-memory FFT processors. / Luo, Hsin Fu; Shieh, Ming Der.
2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 178-179 7216842 (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Efficient memory management scheme for pipelined shared-memory FFT processors

AU - Luo, Hsin Fu

AU - Shieh, Ming Der

PY - 2015/8/20

Y1 - 2015/8/20

N2 - This paper presents an efficient memory management scheme for pipelined shared-memory architectures of the fast Fourier transform (FFT). A multi-path delay commutator (MDC) with a data relocation scheme is developed to merge multiple banks for lowering the area requirement and power dissipation of pipelined shared-memory FFT architectures. Moreover, a generalized memory addressing algorithm that can support mixed-radix MDC architectures is also proposed. The presented architecture outperforms conventional pipelined shared-memory FFT designs, which employ multi-bank memory structures, in terms of the area requirement and power consumption.

AB - This paper presents an efficient memory management scheme for pipelined shared-memory architectures of the fast Fourier transform (FFT). A multi-path delay commutator (MDC) with a data relocation scheme is developed to merge multiple banks for lowering the area requirement and power dissipation of pipelined shared-memory FFT architectures. Moreover, a generalized memory addressing algorithm that can support mixed-radix MDC architectures is also proposed. The presented architecture outperforms conventional pipelined shared-memory FFT designs, which employ multi-bank memory structures, in terms of the area requirement and power consumption.

UR - https://www.scopus.com/pages/publications/84959547378

UR - https://www.scopus.com/pages/publications/84959547378#tab=citedBy

U2 - 10.1109/ICCE-TW.2015.7216842

DO - 10.1109/ICCE-TW.2015.7216842

M3 - Conference contribution

AN - SCOPUS:84959547378

T3 - 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

SP - 178

EP - 179

BT - 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

Y2 - 6 June 2015 through 8 June 2015

ER -

Luo HF, Shieh MD. Efficient memory management scheme for pipelined shared-memory FFT processors. In 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 178-179. 7216842. (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015). doi: 10.1109/ICCE-TW.2015.7216842

Efficient memory management scheme for pipelined shared-memory FFT processors

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