Efficient overdetection elimination of acceptable faults for yield improvement

Kuen Jong Lee, Tong Yu Hsieh, Melvin A. Breuer

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

Acceptable faults in a circuit under test (CUT) refer to those faults that have no or only minor impacts on the performance of the CUT. A circuit with an acceptable fault may be marketable for some specific applications. Therefore, by carefully dealing with these faults during testing, significant yield improvement can be achieved. Previous studies have shown that the patterns generated by a conventional automatic test pattern generation procedure to detect all unacceptable faults also detect many acceptable ones, resulting in a severe loss on achievable yield improvement. In this paper, we present a novel test methodology called multiple test set detection (MTSD) to totally eliminate this overdetection problem. A basic test set generation method is first presented, which depicts a fundamental scheme to generate appropriate test sets for MTSD. We then describe an enhanced test generation method that can significantly reduce the total number of test patterns. Solid theoretical derivations are provided to validate the effectiveness of the proposed methods. Experimental results show that in general an 80%-99% reduction in the number of test patterns can be achieved compared with previous work addressing this problem.

Original languageEnglish
Article number6186858
Pages (from-to)754-764
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume31
Issue number5
DOIs
Publication statusPublished - 2012 May 1

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Networks (circuits)
Automatic test pattern generation
Testing

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

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Efficient overdetection elimination of acceptable faults for yield improvement. / Lee, Kuen Jong; Hsieh, Tong Yu; Breuer, Melvin A.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 5, 6186858, 01.05.2012, p. 754-764.

Research output: Contribution to journalArticle

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