Efficient path metric access for reducing interconnect overhead in viterbi decoders

Ming-Der Shieh, Tai Ping Wang, Chien Ming Wu, Chun Ming Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Efficient management of the path metric memory and minimization of interconnection networks between the memory and add_compare_select unit (ACSU) are always the key concerns on the design and implementation of Viterbi decoders. In this paper, we derive a set of simple equations to partition the memory into P banks such that the equivalent memory bandwidth can be increased with very simple interconnection networks. Compared with the previous work, our proposed approach reveals the following superiority: (1) Each memory bank can be treated as a local memory of a specific ACS; thus, the interconnection network is simplified. (2) The P memory banks can be merged into only two pseudobanks regardless of the number of ACS operations. This not only further reduces the hardware requirements of address generation, but also makes smaller the required memory space.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages4815-4818
Number of pages4
Publication statusPublished - 2006 Dec 1
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 2006 May 212006 May 24

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period06-05-2106-05-24

Fingerprint

Data storage equipment
Hardware
Bandwidth

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Shieh, M-D., Wang, T. P., Wu, C. M., & Huang, C. M. (2006). Efficient path metric access for reducing interconnect overhead in viterbi decoders. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings (pp. 4815-4818). [1693708] (Proceedings - IEEE International Symposium on Circuits and Systems).
Shieh, Ming-Der ; Wang, Tai Ping ; Wu, Chien Ming ; Huang, Chun Ming. / Efficient path metric access for reducing interconnect overhead in viterbi decoders. ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. pp. 4815-4818 (Proceedings - IEEE International Symposium on Circuits and Systems).
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Shieh, M-D, Wang, TP, Wu, CM & Huang, CM 2006, Efficient path metric access for reducing interconnect overhead in viterbi decoders. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693708, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 4815-4818, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 06-05-21.

Efficient path metric access for reducing interconnect overhead in viterbi decoders. / Shieh, Ming-Der; Wang, Tai Ping; Wu, Chien Ming; Huang, Chun Ming.

ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 4815-4818 1693708 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - Efficient management of the path metric memory and minimization of interconnection networks between the memory and add_compare_select unit (ACSU) are always the key concerns on the design and implementation of Viterbi decoders. In this paper, we derive a set of simple equations to partition the memory into P banks such that the equivalent memory bandwidth can be increased with very simple interconnection networks. Compared with the previous work, our proposed approach reveals the following superiority: (1) Each memory bank can be treated as a local memory of a specific ACS; thus, the interconnection network is simplified. (2) The P memory banks can be merged into only two pseudobanks regardless of the number of ACS operations. This not only further reduces the hardware requirements of address generation, but also makes smaller the required memory space.

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Shieh M-D, Wang TP, Wu CM, Huang CM. Efficient path metric access for reducing interconnect overhead in viterbi decoders. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 4815-4818. 1693708. (Proceedings - IEEE International Symposium on Circuits and Systems).