TY - GEN
T1 - Efficient protocol converter generation for system integration
AU - Yang, Der Wei
AU - Shieh, Ming Der
AU - Kuo, Wen Hsuen
AU - Wang, Jonas
PY - 2010
Y1 - 2010
N2 - Integrate intellectual properties (IP's) designed for different protocols is always a troublesome task for system integrators. In this paper, we explore efficient methods to generate protocol converters automatically under the consideration of system performance. For the frequency/phase mismatch, we proposed a modified asynchronous FIFO together with our protocol converter. The generated results are verified in Synopsis Verification IP (VIP) environment. The performance and cost of the resulted converter are as efficient as the manual one, ARM Prime Cell.
AB - Integrate intellectual properties (IP's) designed for different protocols is always a troublesome task for system integrators. In this paper, we explore efficient methods to generate protocol converters automatically under the consideration of system performance. For the frequency/phase mismatch, we proposed a modified asynchronous FIFO together with our protocol converter. The generated results are verified in Synopsis Verification IP (VIP) environment. The performance and cost of the resulted converter are as efficient as the manual one, ARM Prime Cell.
UR - http://www.scopus.com/inward/record.url?scp=79959271873&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79959271873&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2010.5774831
DO - 10.1109/APCCAS.2010.5774831
M3 - Conference contribution
AN - SCOPUS:79959271873
SN - 9781424474561
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 903
EP - 906
BT - Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
T2 - 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Y2 - 6 December 2010 through 9 December 2010
ER -