Abstract
In this paper, efficient architectures for realizing the recursive discrete cosine transform (DCT) and the recursive inverse DCT (IDCT) are proposed. By respectively folding the inputs of the DCT and the outputs of the IDCT, efficient formulations of the DCT and IDCT are derived to construct the transform kernels. The data throughput per transformation is twice that of the existing methods by spending only half of the computational cycles used by the single folding algorithms. To further improve efficiency, the double folding recursive architectures of the DCT and IDCT are developed. The computational cycles of the DCT are half of the single folding method, and the data throughput of the IDCT is twice that of the single folding method. The regular and modular properties of the proposed recursive architectures are suitable for very large scale integration (VLSI) implementation. With high throughput advantage, the proposed structures could be implemented with less power consumption, which could be applied to low rate video in mobile and portable information appliances.
| Original language | English |
|---|---|
| Pages (from-to) | 2665-2669 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Signal Processing |
| Volume | 52 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 2004 Sep 1 |
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All Science Journal Classification (ASJC) codes
- Signal Processing
- Electrical and Electronic Engineering
Cite this
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Efficient recursive structures for forward and inverse discrete cosine transform. / Chen, Che Hong; Liu, Bin Da; Yang, Jar Ferr; Wang, Jiun Lung.
In: IEEE Transactions on Signal Processing, Vol. 52, No. 9, 01.09.2004, p. 2665-2669.Research output: Contribution to journal › Article
TY - JOUR
T1 - Efficient recursive structures for forward and inverse discrete cosine transform
AU - Chen, Che Hong
AU - Liu, Bin Da
AU - Yang, Jar Ferr
AU - Wang, Jiun Lung
PY - 2004/9/1
Y1 - 2004/9/1
N2 - In this paper, efficient architectures for realizing the recursive discrete cosine transform (DCT) and the recursive inverse DCT (IDCT) are proposed. By respectively folding the inputs of the DCT and the outputs of the IDCT, efficient formulations of the DCT and IDCT are derived to construct the transform kernels. The data throughput per transformation is twice that of the existing methods by spending only half of the computational cycles used by the single folding algorithms. To further improve efficiency, the double folding recursive architectures of the DCT and IDCT are developed. The computational cycles of the DCT are half of the single folding method, and the data throughput of the IDCT is twice that of the single folding method. The regular and modular properties of the proposed recursive architectures are suitable for very large scale integration (VLSI) implementation. With high throughput advantage, the proposed structures could be implemented with less power consumption, which could be applied to low rate video in mobile and portable information appliances.
AB - In this paper, efficient architectures for realizing the recursive discrete cosine transform (DCT) and the recursive inverse DCT (IDCT) are proposed. By respectively folding the inputs of the DCT and the outputs of the IDCT, efficient formulations of the DCT and IDCT are derived to construct the transform kernels. The data throughput per transformation is twice that of the existing methods by spending only half of the computational cycles used by the single folding algorithms. To further improve efficiency, the double folding recursive architectures of the DCT and IDCT are developed. The computational cycles of the DCT are half of the single folding method, and the data throughput of the IDCT is twice that of the single folding method. The regular and modular properties of the proposed recursive architectures are suitable for very large scale integration (VLSI) implementation. With high throughput advantage, the proposed structures could be implemented with less power consumption, which could be applied to low rate video in mobile and portable information appliances.
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U2 - 10.1109/TSP.2004.831911
DO - 10.1109/TSP.2004.831911
M3 - Article
AN - SCOPUS:4344700039
VL - 52
SP - 2665
EP - 2669
JO - IEEE Transactions on Signal Processing
JF - IEEE Transactions on Signal Processing
SN - 1053-587X
IS - 9
ER -