Abstract
This paper presents a multi-mode Reed-Solomon decoder design based on the reformulated inversionless Berlekamp-Massey algorithm. We show how to effectively improve the hardware utilization of the decoder and how to simplify the routing network in conventional multi-mode decoder design. The developed coefficient-selector-free multi-mode arrangement, make the decoder area-efficient and gives it a very simple and regular interconnect topology, making the decoder very suitable for VLSI realization. Experimental results show that for codewords of length n < 255 with t-error-correcting capabilities, 0<t≤8, the throughput rate of our decoder, implemented on a 0.18um process, can reach 3.2 Gbps at an operating frequency of 400 MHz with a total gate count of 22,931. Moreover, the hardware overhead of the developed multi-mode decoder is only 13.4% compared to our single-mode design for t = 8. Compared to the existing work based on the extended Euclidean algorithm for multi-mode applications, our design provides both area and speed advantages. Using the developed generator, we implemented a multi-mode decoder that can be applied to seven existing standards to demonstrate the regularity and flexibility of our design.
| Original language | English |
|---|---|
| Pages (from-to) | 503-516 |
| Number of pages | 14 |
| Journal | International Journal of Electrical Engineering |
| Volume | 16 |
| Issue number | 6 |
| Publication status | Published - 2009 Dec |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Efficient reed-solomon decoder design for multi-mode applications. / Shieh, Ming-Der; Lu, Yung Kuei; Chung, Shen Ming.
In: International Journal of Electrical Engineering, Vol. 16, No. 6, 12.2009, p. 503-516.Research output: Contribution to journal › Article
TY - JOUR
T1 - Efficient reed-solomon decoder design for multi-mode applications
AU - Shieh, Ming-Der
AU - Lu, Yung Kuei
AU - Chung, Shen Ming
PY - 2009/12
Y1 - 2009/12
N2 - This paper presents a multi-mode Reed-Solomon decoder design based on the reformulated inversionless Berlekamp-Massey algorithm. We show how to effectively improve the hardware utilization of the decoder and how to simplify the routing network in conventional multi-mode decoder design. The developed coefficient-selector-free multi-mode arrangement, make the decoder area-efficient and gives it a very simple and regular interconnect topology, making the decoder very suitable for VLSI realization. Experimental results show that for codewords of length n < 255 with t-error-correcting capabilities, 0
AB - This paper presents a multi-mode Reed-Solomon decoder design based on the reformulated inversionless Berlekamp-Massey algorithm. We show how to effectively improve the hardware utilization of the decoder and how to simplify the routing network in conventional multi-mode decoder design. The developed coefficient-selector-free multi-mode arrangement, make the decoder area-efficient and gives it a very simple and regular interconnect topology, making the decoder very suitable for VLSI realization. Experimental results show that for codewords of length n < 255 with t-error-correcting capabilities, 0
UR - http://www.scopus.com/inward/record.url?scp=76249107154&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=76249107154&partnerID=8YFLogxK
M3 - Article
VL - 16
SP - 503
EP - 516
JO - International Journal of Electrical Engineering
JF - International Journal of Electrical Engineering
SN - 1812-3031
IS - 6
ER -