Efficient test scheduling for hierarchical core based design

Tai Ping Wang, Cheng Yu Tsai, Ming-Der Shieh, Kuen-Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Core-based system-on-chip (SOC) design methodology integrates heterogeneous technology from multiple sources. As fabrication technology and design technique make progress, today's SOC may become tomorrow's embedded core. The design hierarchy of the SOC results in test integration challenges. The proposed SOC test scheduling technique is used to minimize the test application time of the SOC with hierarchical embedded cores. Unlike previous work in this area that assumes the SOC design hierarchy to be flattened, the proposed technique takes into account the design hierarchy constraints including the dedicated TAM assignment and fixed I/O pin number of the hierarchical cores. Experimental results are presented for ITC'02 SOC Test Benchmarks with about 5.73% (on average) test application time overhead compared with the flattened test scheduling scheme.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages200-203
Number of pages4
Volume2005
DOIs
Publication statusPublished - 2005
Event2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
Duration: 2005 Apr 272005 Apr 29

Other

Other2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
CountryTaiwan
CityHsinchu
Period05-04-2705-04-29

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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