Efficient VLSI design for SIFT feature description

Yi Ming Lin, Chun Hsien Yeh, Sheng Hung Yen, Ching Hsuan Ma, Pei Yin Chen, C. C. Jay Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

The scale invariant feature transform (SIFT) is a very efficient algorithm to extract and describe distinctive invariant features from images, and usually applied for many image applications such as object recognition, robotic mapping, and navigation. In the SIFT computation, the complexity of the feature description is quite high. Hence, it is desirable to have an efficient VLSI architecture to compute the feature descriptor quickly. We first investigate the performance analysis for SIFT and then employ the proper hardware circuit to implement the feature description process. Besides, the pipe lining technique is adopted to increase the speed of our design. Synthesis results show that the proposed circuit contains 555,062 transistors by using the TSMC 0.13/lm cell library. It works with a clock rate of 200 MHz and can support the throughput rate of about 65300 SIFT descriptors per second in real time.

Original languageEnglish
Title of host publication2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
Pages48-51
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
Duration: 2010 Nov 182010 Nov 19

Publication series

Name2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other2010 International Symposium on Next-Generation Electronics, ISNE 2010
CountryTaiwan
CityKaohsiung
Period10-11-1810-11-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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