The scale invariant feature transform (SIFT) is a very efficient algorithm to extract and describe distinctive invariant features from images, and usually applied for many image applications such as object recognition, robotic mapping, and navigation. In the SIFT computation, the complexity of the feature description is quite high. Hence, it is desirable to have an efficient VLSI architecture to compute the feature descriptor quickly. We first investigate the performance analysis for SIFT and then employ the proper hardware circuit to implement the feature description process. Besides, the pipe lining technique is adopted to increase the speed of our design. Synthesis results show that the proposed circuit contains 555,062 transistors by using the TSMC 0.13/lm cell library. It works with a clock rate of 200 MHz and can support the throughput rate of about 65300 SIFT descriptors per second in real time.