The memory cores are essential for a system-on-a-chip (SOC). To test the memory cores, in this paper we propose a generalized embedded test pattern generator for any march algorithm. Without loss of functionality of the march algorithm, we also present a systematic procedure with a short time complexity to reduce the hardware cost of the test pattern generator.
|Number of pages||4|
|Journal||International Symposium on VLSI Technology, Systems, and Applications, Proceedings|
|Publication status||Published - 1999|
All Science Journal Classification (ASJC) codes