TY - GEN
T1 - Embedded memory diagnostic data compression using differential address
AU - Su, Chin Lung
AU - Huang, Rei Fu
AU - Wu, Cheng Wen
AU - Chang, Yeong Jar
AU - Lin, Shen Tien
AU - Wu, Wen Ching
PY - 2005/12/1
Y1 - 2005/12/1
N2 - Embedded memory diagnostics is normally done by the built-in self-diagnosis (BISD) hardware, which collects and sends the diagnostic data to the external tester. The cost of the diagnosis process highly depends on the data volumn sent between the chip under test and the tester, since the transmission time and the tester capture memory are major cost factors. We propose a memory BISD design using differential addressing, as well as a method for evaluating and choosing a proper differential address level. Based on our previous work on pattern identification BISD and syndrome compression design, the proposed differential address compression scheme further reduces the diagnostic data volumn. Experimental results show that the BISD design is cost-effective.
AB - Embedded memory diagnostics is normally done by the built-in self-diagnosis (BISD) hardware, which collects and sends the diagnostic data to the external tester. The cost of the diagnosis process highly depends on the data volumn sent between the chip under test and the tester, since the transmission time and the tester capture memory are major cost factors. We propose a memory BISD design using differential addressing, as well as a method for evaluating and choosing a proper differential address level. Based on our previous work on pattern identification BISD and syndrome compression design, the proposed differential address compression scheme further reduces the diagnostic data volumn. Experimental results show that the BISD design is cost-effective.
UR - http://www.scopus.com/inward/record.url?scp=33745467785&partnerID=8YFLogxK
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U2 - 10.1109/VDAT.2005.1500009
DO - 10.1109/VDAT.2005.1500009
M3 - Conference contribution
AN - SCOPUS:33745467785
SN - 0780390601
SN - 9780780390607
T3 - 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
SP - 20
EP - 23
BT - 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
T2 - 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Y2 - 27 April 2005 through 29 April 2005
ER -