Abstract
Incorporating power management during partitioning at the system level contributes considerably to energy efficient architecture. Designers commonly implement systems as a mix of partitioning blocks of various sizes, connected using bus interconnection architecture. Therefore, the use of a partitioning approach that partitions a system with the greatest possible idle time on a dedicated interconnection architecture has become unpractical for power management development. This work presents a novel energy-aware hardware clustering algorithm with a performance estimator for on-chip bus based architectures during high level synthesis, to enhance the quality of solutions for implementing power management systems. Experimental results obtained in four cases reveal that the proposed strategy generates a wide range of cost-effective solutions and is highly effective for today's hardware systems.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 |
| Pages | 345-348 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2011 Jun 28 |
| Event | 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan Duration: 2011 Apr 25 → 2011 Apr 28 |
Publication series
| Name | Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 |
|---|
Other
| Other | 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 |
|---|---|
| Country | Taiwan |
| City | Hsinchu |
| Period | 11-04-25 → 11-04-28 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
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Energy-aware partitioning for on-chip bus architecture using a multi-objective genetic algorithm. / Chiou, Lih Yih; Chen, Yi Siou; Jian, Ya Lun.
Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 345-348 5783544 (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Energy-aware partitioning for on-chip bus architecture using a multi-objective genetic algorithm
AU - Chiou, Lih Yih
AU - Chen, Yi Siou
AU - Jian, Ya Lun
PY - 2011/6/28
Y1 - 2011/6/28
N2 - Incorporating power management during partitioning at the system level contributes considerably to energy efficient architecture. Designers commonly implement systems as a mix of partitioning blocks of various sizes, connected using bus interconnection architecture. Therefore, the use of a partitioning approach that partitions a system with the greatest possible idle time on a dedicated interconnection architecture has become unpractical for power management development. This work presents a novel energy-aware hardware clustering algorithm with a performance estimator for on-chip bus based architectures during high level synthesis, to enhance the quality of solutions for implementing power management systems. Experimental results obtained in four cases reveal that the proposed strategy generates a wide range of cost-effective solutions and is highly effective for today's hardware systems.
AB - Incorporating power management during partitioning at the system level contributes considerably to energy efficient architecture. Designers commonly implement systems as a mix of partitioning blocks of various sizes, connected using bus interconnection architecture. Therefore, the use of a partitioning approach that partitions a system with the greatest possible idle time on a dedicated interconnection architecture has become unpractical for power management development. This work presents a novel energy-aware hardware clustering algorithm with a performance estimator for on-chip bus based architectures during high level synthesis, to enhance the quality of solutions for implementing power management systems. Experimental results obtained in four cases reveal that the proposed strategy generates a wide range of cost-effective solutions and is highly effective for today's hardware systems.
UR - http://www.scopus.com/inward/record.url?scp=79959504398&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79959504398&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2011.5783544
DO - 10.1109/VDAT.2011.5783544
M3 - Conference contribution
AN - SCOPUS:79959504398
SN - 9781424484997
T3 - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
SP - 345
EP - 348
BT - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
ER -