Energy-aware partitioning for on-chip bus architecture using a multi-objective genetic algorithm

Lih Yih Chiou, Yi Siou Chen, Ya Lun Jian

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Incorporating power management during partitioning at the system level contributes considerably to energy efficient architecture. Designers commonly implement systems as a mix of partitioning blocks of various sizes, connected using bus interconnection architecture. Therefore, the use of a partitioning approach that partitions a system with the greatest possible idle time on a dedicated interconnection architecture has become unpractical for power management development. This work presents a novel energy-aware hardware clustering algorithm with a performance estimator for on-chip bus based architectures during high level synthesis, to enhance the quality of solutions for implementing power management systems. Experimental results obtained in four cases reveal that the proposed strategy generates a wide range of cost-effective solutions and is highly effective for today's hardware systems.

Original languageEnglish
Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages345-348
Number of pages4
DOIs
Publication statusPublished - 2011 Jun 28
Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
Duration: 2011 Apr 252011 Apr 28

Publication series

NameProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Other

Other2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
CountryTaiwan
CityHsinchu
Period11-04-2511-04-28

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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