Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

In this paper, we propose two novel dual edge-triggered flip-flops. One design eliminates redundant transitions of internal nodes when current data is the same as the previous one. This has the least power delay product compared to other dual edge-triggered flip-flops in all range of possible data switching activity and its delay is also the smallest. The other proposed flip-flop disables internal clocked transistors. When data switching activity is within 20%, it has the least power consumption.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages4329-4332
Number of pages4
Publication statusPublished - 2006 Dec 1
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 2006 May 212006 May 24

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period06-05-2106-05-24

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Liu, Y. T., Chiou, L-Y., & Chang, S-J. (2006). Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings (pp. 4329-4332). [1693587] (Proceedings - IEEE International Symposium on Circuits and Systems).