TY - JOUR
T1 - Energy-efficient dual-edge-triggered level converting flip flops with symmetry in setup times and insensitivity to output parasitics
AU - Chiou, Lih Yih
AU - Luo, Shien Chun
N1 - Funding Information:
Manuscript received March 28, 2008; revised August 20, 2008. First published April 14, 2009; current version published October 21, 2009. This work was supported in part by the National Science Council under Grant NSC 97-2220-E-006-006 and Grant NSC 96-2220-E-006-003.
PY - 2009/11
Y1 - 2009/11
N2 - Level converting flip-flops (LCFFs) are crucial components for multisupply systems as interfaces between different voltage islands. The proposed energy-efficient LCFFs reduce the power consumption of clock networks with dual-edge triggering, support sleep mode of power management mechanisms with data retention, and have symmetry in setup times and insensitivity to output parasitics. With all these features, the proposed LCFFs have 19% and 38% lower power-delay product than the conventional LCFF, as demonstrated by postlayout simulation results.
AB - Level converting flip-flops (LCFFs) are crucial components for multisupply systems as interfaces between different voltage islands. The proposed energy-efficient LCFFs reduce the power consumption of clock networks with dual-edge triggering, support sleep mode of power management mechanisms with data retention, and have symmetry in setup times and insensitivity to output parasitics. With all these features, the proposed LCFFs have 19% and 38% lower power-delay product than the conventional LCFF, as demonstrated by postlayout simulation results.
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U2 - 10.1109/TVLSI.2008.2007959
DO - 10.1109/TVLSI.2008.2007959
M3 - Article
AN - SCOPUS:70350618331
SN - 1063-8210
VL - 17
SP - 1659
EP - 1663
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 11
M1 - 4814496
ER -