Energy scaling of spintronics for information processing - A new paradigm towards intelligent systems

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The talk will first give a brief overview of the energy scaling challenge of today s CMOS and its derivatives, including FINFET, TUNNET, etc. Several potential spintronics devices, which are being pursued by the Nanoelectronics Research Initiative (NRI), along with benchmark efforts will be briefly described.1 Then I will describe the physics and principles as well as advantages and impact of magnetic devices in terms of their low switching energy, high speed, high endurance, and scalability. In particular, the energy dissipation of spin transfer torque (STT) devices will be described for embedded memory applications when benchmarked with scaled CMOS. Recent progress of spin-orbital interactions for the benefit of energy scaling for potential spintronics devices will be discussed, to improve energy efficient switching via polarized spins. In particular, the new discovered engineering of spin-orbit interaction at the interface will be delineated.2'3 Recently, it was shown to possibly use electric fields to control magnetic properties of metallic ferromagnetic layers at the metal/insulator interface. For the latter, we will describe a couple of fundamental mechanisms of voltage control of magnetic moment and direction at the metallic surface. Specifically electric field control of metallic magnetism via engineering of the spin-orbit interactions at the metallic interface will be discussed. This leads to electric-field or voltage controlled magneto-electric (ME) memory (MeRAM) 4, resulting in much reduced energy dissipation for switching as well as improved scaling and density. The dynamics of the switching as well as additional physical processes in improving the switching process will be outlined. Additionally the recent progress in using spin Hall effect with high spin orbital metals5 as well as topological insulators will be shown to produce large torque for further reducing energy in switching nanomagnets. Energy scaling will be addressed. Further advances are possible by adopting the spin wave bus (SWB) concept - the use of spin waves for logic and interconnect6 as an alternative for CMOS. This SWB along with other related spin based logic devices will be benchmarked against CMOS in terms of energy dissipation. With low energy, high density embedded memory, and spin wave bus, it may be possible to construct a new type of neuromorphic information processing electronics. Spintronic memory may be integrated directly on top of front-end processed CMOS; further on, it is possible to incorporate SWB to enable new generations of nonvolatile instant-on electronics and a new paradigm of intelligent nano-systems.7 Other device possibilities using new materials and their emerging potentials will be discussed.

Original languageEnglish
Title of host publication72nd Device Research Conference, DRC 2014 - Conference Digest
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Print)9781479954056
Publication statusPublished - 2014
Event72nd Device Research Conference, DRC 2014 - Santa Barbara, CA, United States
Duration: 2014 Jun 222014 Jun 25

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770


Other72nd Device Research Conference, DRC 2014
Country/TerritoryUnited States
CitySanta Barbara, CA

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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