@inproceedings{a801e2f9991345f0845659f6e1f18c78,
title = "Enhancement of the weight cell utilization for CMAC neural networks: Architecture design and hardware implementation",
abstract = "CMAC neural network model has the advantages of fast learning and insensitivity to the order of presentation of training data. However, it may suffer from a huge storage requirement for realizing the weight cell memory. In this paper, we propose a memory banking structure and a direct weight cell address mapping scheme, which can sharply reduce the required address space of weight cell memory. This mapping scheme also exhibits a fast computation speed in generating weight cell addresses. Besides, a pipelined architecture is developed to realize the CMAC chip. To efficiently manage design complexity and increase design productivity and maintainability, a high-level synthesis technique is adopted to perform the task of logic design of the CMAC chip.",
author = "Ker, {Jar Shone} and Wen, {Rong Chang} and Kuo, {Yau Hwang} and Liu, {Bin Da}",
note = "Publisher Copyright: {\textcopyright} 1994 IEEE.; 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, ICMNN 1994 ; Conference date: 26-09-1994",
year = "1994",
doi = "10.1109/ICMNN.1994.593716",
language = "English",
series = "Proceedings of the 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, ICMNN 1994",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "244--251",
booktitle = "Proceedings of the 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, ICMNN 1994",
address = "United States",
}