Error catch and analysis for semiconductor memories using March tests

Chi Feng Wu; Chih Tsun Huang; Chih Wea Wang; Kuo Liang Cheng; Cheng Wen Wu

doi:10.1109/ICCAD.2000.896516

Error catch and analysis for semiconductor memories using March tests

Chi Feng Wu, Chih Tsun Huang, Chih Wea Wang, Kuo Liang Cheng, Cheng Wen Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

45 Citations (Scopus)

Abstract

We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and an error analyzer (ERA). We use TAGS to generate a set of test algorithms of different lengths and diagnostic resolutions for the memory under test, and use RAMSES to generate the March dictionary for each test algorithm. With the March dictionaries, ERA is able to support March algorithms for easy diagnosis of faulty RAMs. Legacy test algorithms also can be reused. When integrated with a RAM tester, our ECA system can generate RAM bitmaps that are similar to the RAM layout. The bitmaps provide detail information about the error locations and faults causing thex errors. Based on the information, diagnosis of the RAM chips for-yield and reliability improvement can be done more easily.

Original language	English
Title of host publication	IEEE/ACM International Conference on Computer Aided Design
Subtitle of host publication	A Conference for the EE CAD Professional, ICCAD 2000
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	468-471
Number of pages	4
ISBN (Electronic)	0780364457
DOIs	https://doi.org/10.1109/ICCAD.2000.896516
Publication status	Published - 2000 Jan 1
Event	IEEE/ACM International Conference on Computer Aided Design, ICCAD 2000 - San Jose, United States Duration: 2000 Nov 5 → 2000 Nov 9

Publication series

Name	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Volume	2000-January
ISSN (Print)	1092-3152

Conference

Conference	IEEE/ACM International Conference on Computer Aided Design, ICCAD 2000
Country/Territory	United States
City	San Jose
Period	00-11-05 → 00-11-09

All Science Journal Classification (ASJC) codes

Software
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1109/ICCAD.2000.896516

Cite this

Wu, C. F., Huang, C. T., Wang, C. W., Cheng, K. L., & Wu, C. W. (2000). Error catch and analysis for semiconductor memories using March tests. In IEEE/ACM International Conference on Computer Aided Design: A Conference for the EE CAD Professional, ICCAD 2000 (pp. 468-471). Article 896516 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2000-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCAD.2000.896516

Wu, Chi Feng ; Huang, Chih Tsun ; Wang, Chih Wea et al. / Error catch and analysis for semiconductor memories using March tests. IEEE/ACM International Conference on Computer Aided Design: A Conference for the EE CAD Professional, ICCAD 2000. Institute of Electrical and Electronics Engineers Inc., 2000. pp. 468-471 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

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title = "Error catch and analysis for semiconductor memories using March tests",

abstract = "We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and an error analyzer (ERA). We use TAGS to generate a set of test algorithms of different lengths and diagnostic resolutions for the memory under test, and use RAMSES to generate the March dictionary for each test algorithm. With the March dictionaries, ERA is able to support March algorithms for easy diagnosis of faulty RAMs. Legacy test algorithms also can be reused. When integrated with a RAM tester, our ECA system can generate RAM bitmaps that are similar to the RAM layout. The bitmaps provide detail information about the error locations and faults causing thex errors. Based on the information, diagnosis of the RAM chips for-yield and reliability improvement can be done more easily.",

author = "Wu, {Chi Feng} and Huang, {Chih Tsun} and Wang, {Chih Wea} and Cheng, {Kuo Liang} and Wu, {Cheng Wen}",

year = "2000",

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Wu, CF, Huang, CT, Wang, CW, Cheng, KL & Wu, CW 2000, Error catch and analysis for semiconductor memories using March tests. in IEEE/ACM International Conference on Computer Aided Design: A Conference for the EE CAD Professional, ICCAD 2000., 896516, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, vol. 2000-January, Institute of Electrical and Electronics Engineers Inc., pp. 468-471, IEEE/ACM International Conference on Computer Aided Design, ICCAD 2000, San Jose, United States, 00-11-05. https://doi.org/10.1109/ICCAD.2000.896516

Error catch and analysis for semiconductor memories using March tests. / Wu, Chi Feng; Huang, Chih Tsun; Wang, Chih Wea et al.
IEEE/ACM International Conference on Computer Aided Design: A Conference for the EE CAD Professional, ICCAD 2000. Institute of Electrical and Electronics Engineers Inc., 2000. p. 468-471 896516 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2000-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and an error analyzer (ERA). We use TAGS to generate a set of test algorithms of different lengths and diagnostic resolutions for the memory under test, and use RAMSES to generate the March dictionary for each test algorithm. With the March dictionaries, ERA is able to support March algorithms for easy diagnosis of faulty RAMs. Legacy test algorithms also can be reused. When integrated with a RAM tester, our ECA system can generate RAM bitmaps that are similar to the RAM layout. The bitmaps provide detail information about the error locations and faults causing thex errors. Based on the information, diagnosis of the RAM chips for-yield and reliability improvement can be done more easily.

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Wu CF, Huang CT, Wang CW, Cheng KL, Wu CW. Error catch and analysis for semiconductor memories using March tests. In IEEE/ACM International Conference on Computer Aided Design: A Conference for the EE CAD Professional, ICCAD 2000. Institute of Electrical and Electronics Engineers Inc. 2000. p. 468-471. 896516. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). doi: 10.1109/ICCAD.2000.896516

Error catch and analysis for semiconductor memories using March tests

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