Error catch and analysis for semiconductor memories using March tests

Chi Feng Wu, Chih Tsun Huang, Chih Wea Wang, Kuo Liang Cheng, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

45 Citations (Scopus)


We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and an error analyzer (ERA). We use TAGS to generate a set of test algorithms of different lengths and diagnostic resolutions for the memory under test, and use RAMSES to generate the March dictionary for each test algorithm. With the March dictionaries, ERA is able to support March algorithms for easy diagnosis of faulty RAMs. Legacy test algorithms also can be reused. When integrated with a RAM tester, our ECA system can generate RAM bitmaps that are similar to the RAM layout. The bitmaps provide detail information about the error locations and faults causing thex errors. Based on the information, diagnosis of the RAM chips for-yield and reliability improvement can be done more easily.

Original languageEnglish
Title of host publicationIEEE/ACM International Conference on Computer Aided Design
Subtitle of host publicationA Conference for the EE CAD Professional, ICCAD 2000
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)0780364457
Publication statusPublished - 2000 Jan 1
EventIEEE/ACM International Conference on Computer Aided Design, ICCAD 2000 - San Jose, United States
Duration: 2000 Nov 52000 Nov 9

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152


ConferenceIEEE/ACM International Conference on Computer Aided Design, ICCAD 2000
Country/TerritoryUnited States
CitySan Jose

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design


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