Evaluation of sequential-in-random-out memory device

C. Y. Chang; C. K. Shieh; T. W. Hou

doi:10.1049/el:19950454

Evaluation of sequential-in-random-out memory device

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Abstract

The buffering of data is a potential bottleneck to performance. In general, the buffer can be implemented either by FIFO or dual-port RAM, which are both two-port memory devices. In the Letter a classification of buffers is proposed. According to the classification, a new two-port memory device with the sequential-in-random-out feature is introduced. Simulation results show that 45% time, at most, could be saved, as compared to a FIFO buffer.

Original language	English
Pages (from-to)	620-621
Number of pages	2
Journal	Electronics Letters
Volume	31
Issue number	8
DOIs	https://doi.org/10.1049/el:19950454
Publication status	Published - 1995 Apr 13

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el:19950454

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abstract = "The buffering of data is a potential bottleneck to performance. In general, the buffer can be implemented either by FIFO or dual-port RAM, which are both two-port memory devices. In the Letter a classification of buffers is proposed. According to the classification, a new two-port memory device with the sequential-in-random-out feature is introduced. Simulation results show that 45% time, at most, could be saved, as compared to a FIFO buffer.",

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Evaluation of sequential-in-random-out memory device

Abstract

All Science Journal Classification (ASJC) codes

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