TY - GEN
T1 - Experimental/numerical analysis of halogen-free printed circuit board assembly under board level drop test
AU - Zhan, Chau Jie
AU - Chang, Hung Jen
AU - Chang, Tao Chih
AU - Chou, Jung Hua
PY - 2009/12/1
Y1 - 2009/12/1
N2 - After the adoption of lead-free electronic products, the halogen-free electronic products are expected to increase in the coming years for environmental protection and green electronics. Currently, for evaluating the drop resistance of handheld electronic products, the board level drop test method is typically employed. In this study, the finite elements analysis was used to analyze the drop responses of totally halogen-free PCBA and the simulation results were verified by drop tests. The outer layers of the halogen-free test board were built-up by resin coated copper (RCC) material. According to the JESD22-B111 standard, five PBGA components with Sn-4Ag-0.5Cu solder balls were mounted on the test board by the Sn-1Ag-0.5Cu solder paste. The ANASYS software was employed to analyze the stress distribution in the joint structures which contained the solder ball, copper pad, and build-up material during drop impacts. The sub-modeling simulation method was used to improve the accuracy and convergence of the simulation results. In addition, by using the support excitation scheme, the contact moment in the impact process during the drop test was translated into effective support excitation loads to simplify the analysis. From the drop test results, failure analysis showed that most of the fractures occurred around the pad on the test board first and then cracks propagated across the outer build-up material. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. The simulation revealed that the maximum normal stress was located at the outmost solder balls in the PCB side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.
AB - After the adoption of lead-free electronic products, the halogen-free electronic products are expected to increase in the coming years for environmental protection and green electronics. Currently, for evaluating the drop resistance of handheld electronic products, the board level drop test method is typically employed. In this study, the finite elements analysis was used to analyze the drop responses of totally halogen-free PCBA and the simulation results were verified by drop tests. The outer layers of the halogen-free test board were built-up by resin coated copper (RCC) material. According to the JESD22-B111 standard, five PBGA components with Sn-4Ag-0.5Cu solder balls were mounted on the test board by the Sn-1Ag-0.5Cu solder paste. The ANASYS software was employed to analyze the stress distribution in the joint structures which contained the solder ball, copper pad, and build-up material during drop impacts. The sub-modeling simulation method was used to improve the accuracy and convergence of the simulation results. In addition, by using the support excitation scheme, the contact moment in the impact process during the drop test was translated into effective support excitation loads to simplify the analysis. From the drop test results, failure analysis showed that most of the fractures occurred around the pad on the test board first and then cracks propagated across the outer build-up material. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. The simulation revealed that the maximum normal stress was located at the outmost solder balls in the PCB side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.
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U2 - 10.1109/IMPACT.2009.5382197
DO - 10.1109/IMPACT.2009.5382197
M3 - Conference contribution
AN - SCOPUS:77950848603
SN - 9781424443413
T3 - IMPACT Conference 2009 International 3D IC Conference - Proceedings
SP - 381
EP - 384
BT - IMPACT Conference 2009 International 3D IC Conference - Proceedings
T2 - IMPACT Conference 2009 International 3D IC Conference
Y2 - 21 October 2009 through 23 October 2009
ER -