Exploiting parallelism of MPEG-4 decoder with dataflow programming on multicore processor

Zhong Ho Chen, Ta Chun Chen, Jung Yin Chien, Wen-Yu Su, Ce-Kuen Shieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multicore processor provides large computation capability but also involves the complicate parallel programming. One of major considerations in parallel programming is the performance. Traditional design methodologies which usually start a design on a selected platform spend a lot of effort and time on tuning performance and debugging. When platform is changed even with different number of cores, considerable redesign effort is required. Hence a flexible design methodology is necessary. In this paper, a design methodology is presented for video codec, by using MPEG-4 SP decoder as an example, on multicore processor. The parallelisms of MPEG-4 decoder are discussed and exposed with the dataflow model. The dataflow model provides a high-level abstraction of underlying hardware. Computation and communication of MPEG-4 decoder are separated and represented as modules and channels, respectively. It is possible to synthesize the model targeting to either dedicate hardware or software on multiprocessor. To map the high level dataflow model to Cell processor, the mapping flow, including offline profiling, task allocation and runtime libraries, are developed. According to the profiling results, the allocation algorithm could allocate tasks on multiprocessors as balanced as possible. An efficient synchronization mechanism on Cell processor is also proposed. We also discuss the impact of the model and the mapping flow corresponding to decoding speed. The results show that the proposed methodology gets considerable performance boost when the number of cores is increased.

Original languageEnglish
Title of host publicationProceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010
Pages367-373
Number of pages7
DOIs
Publication statusPublished - 2010 Dec 1
EventInternational Symposium on Parallel and Distributed Processing with Applications, ISPA 2010 - Taipei, Taiwan
Duration: 2010 Sep 62010 Sep 9

Publication series

NameProceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010

Other

OtherInternational Symposium on Parallel and Distributed Processing with Applications, ISPA 2010
CountryTaiwan
CityTaipei
Period10-09-0610-09-09

Fingerprint

Parallel programming
Hardware
Decoding
Synchronization
Tuning
Communication

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Computer Science Applications

Cite this

Chen, Z. H., Chen, T. C., Chien, J. Y., Su, W-Y., & Shieh, C-K. (2010). Exploiting parallelism of MPEG-4 decoder with dataflow programming on multicore processor. In Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010 (pp. 367-373). [5634354] (Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010). https://doi.org/10.1109/ISPA.2010.9
Chen, Zhong Ho ; Chen, Ta Chun ; Chien, Jung Yin ; Su, Wen-Yu ; Shieh, Ce-Kuen. / Exploiting parallelism of MPEG-4 decoder with dataflow programming on multicore processor. Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010. 2010. pp. 367-373 (Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010).
@inproceedings{b55db088b462494fbd095936ddc81291,
title = "Exploiting parallelism of MPEG-4 decoder with dataflow programming on multicore processor",
abstract = "Multicore processor provides large computation capability but also involves the complicate parallel programming. One of major considerations in parallel programming is the performance. Traditional design methodologies which usually start a design on a selected platform spend a lot of effort and time on tuning performance and debugging. When platform is changed even with different number of cores, considerable redesign effort is required. Hence a flexible design methodology is necessary. In this paper, a design methodology is presented for video codec, by using MPEG-4 SP decoder as an example, on multicore processor. The parallelisms of MPEG-4 decoder are discussed and exposed with the dataflow model. The dataflow model provides a high-level abstraction of underlying hardware. Computation and communication of MPEG-4 decoder are separated and represented as modules and channels, respectively. It is possible to synthesize the model targeting to either dedicate hardware or software on multiprocessor. To map the high level dataflow model to Cell processor, the mapping flow, including offline profiling, task allocation and runtime libraries, are developed. According to the profiling results, the allocation algorithm could allocate tasks on multiprocessors as balanced as possible. An efficient synchronization mechanism on Cell processor is also proposed. We also discuss the impact of the model and the mapping flow corresponding to decoding speed. The results show that the proposed methodology gets considerable performance boost when the number of cores is increased.",
author = "Chen, {Zhong Ho} and Chen, {Ta Chun} and Chien, {Jung Yin} and Wen-Yu Su and Ce-Kuen Shieh",
year = "2010",
month = "12",
day = "1",
doi = "10.1109/ISPA.2010.9",
language = "English",
isbn = "9780769541907",
series = "Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010",
pages = "367--373",
booktitle = "Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010",

}

Chen, ZH, Chen, TC, Chien, JY, Su, W-Y & Shieh, C-K 2010, Exploiting parallelism of MPEG-4 decoder with dataflow programming on multicore processor. in Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010., 5634354, Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010, pp. 367-373, International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010, Taipei, Taiwan, 10-09-06. https://doi.org/10.1109/ISPA.2010.9

Exploiting parallelism of MPEG-4 decoder with dataflow programming on multicore processor. / Chen, Zhong Ho; Chen, Ta Chun; Chien, Jung Yin; Su, Wen-Yu; Shieh, Ce-Kuen.

Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010. 2010. p. 367-373 5634354 (Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Exploiting parallelism of MPEG-4 decoder with dataflow programming on multicore processor

AU - Chen, Zhong Ho

AU - Chen, Ta Chun

AU - Chien, Jung Yin

AU - Su, Wen-Yu

AU - Shieh, Ce-Kuen

PY - 2010/12/1

Y1 - 2010/12/1

N2 - Multicore processor provides large computation capability but also involves the complicate parallel programming. One of major considerations in parallel programming is the performance. Traditional design methodologies which usually start a design on a selected platform spend a lot of effort and time on tuning performance and debugging. When platform is changed even with different number of cores, considerable redesign effort is required. Hence a flexible design methodology is necessary. In this paper, a design methodology is presented for video codec, by using MPEG-4 SP decoder as an example, on multicore processor. The parallelisms of MPEG-4 decoder are discussed and exposed with the dataflow model. The dataflow model provides a high-level abstraction of underlying hardware. Computation and communication of MPEG-4 decoder are separated and represented as modules and channels, respectively. It is possible to synthesize the model targeting to either dedicate hardware or software on multiprocessor. To map the high level dataflow model to Cell processor, the mapping flow, including offline profiling, task allocation and runtime libraries, are developed. According to the profiling results, the allocation algorithm could allocate tasks on multiprocessors as balanced as possible. An efficient synchronization mechanism on Cell processor is also proposed. We also discuss the impact of the model and the mapping flow corresponding to decoding speed. The results show that the proposed methodology gets considerable performance boost when the number of cores is increased.

AB - Multicore processor provides large computation capability but also involves the complicate parallel programming. One of major considerations in parallel programming is the performance. Traditional design methodologies which usually start a design on a selected platform spend a lot of effort and time on tuning performance and debugging. When platform is changed even with different number of cores, considerable redesign effort is required. Hence a flexible design methodology is necessary. In this paper, a design methodology is presented for video codec, by using MPEG-4 SP decoder as an example, on multicore processor. The parallelisms of MPEG-4 decoder are discussed and exposed with the dataflow model. The dataflow model provides a high-level abstraction of underlying hardware. Computation and communication of MPEG-4 decoder are separated and represented as modules and channels, respectively. It is possible to synthesize the model targeting to either dedicate hardware or software on multiprocessor. To map the high level dataflow model to Cell processor, the mapping flow, including offline profiling, task allocation and runtime libraries, are developed. According to the profiling results, the allocation algorithm could allocate tasks on multiprocessors as balanced as possible. An efficient synchronization mechanism on Cell processor is also proposed. We also discuss the impact of the model and the mapping flow corresponding to decoding speed. The results show that the proposed methodology gets considerable performance boost when the number of cores is increased.

UR - http://www.scopus.com/inward/record.url?scp=79952084173&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79952084173&partnerID=8YFLogxK

U2 - 10.1109/ISPA.2010.9

DO - 10.1109/ISPA.2010.9

M3 - Conference contribution

SN - 9780769541907

T3 - Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010

SP - 367

EP - 373

BT - Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010

ER -

Chen ZH, Chen TC, Chien JY, Su W-Y, Shieh C-K. Exploiting parallelism of MPEG-4 decoder with dataflow programming on multicore processor. In Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010. 2010. p. 367-373. 5634354. (Proceedings - International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010). https://doi.org/10.1109/ISPA.2010.9