Exploring transistor width effect on stress-induced performance improvement in PMOSFET with SiGe source/drain

Xin Wang, M. Huang, C. Bowen, L. Adam, S. Singh, C. Chiu, J. Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Stress distribution in the Si channel regions of SiGe source/drain PMOSFETs with various widths is studied by 3D simulations. The width dependence of performance improvement is analyzed via device simulations.

Original languageEnglish
Title of host publication2005 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2005
Pages323-326
Number of pages4
Publication statusPublished - 2005
Event2005 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2005 - Tokyo, Japan
Duration: 2005 Sept 12005 Sept 3

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume2005

Other

Other2005 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2005
Country/TerritoryJapan
CityTokyo
Period05-09-0105-09-03

All Science Journal Classification (ASJC) codes

  • General Engineering

Fingerprint

Dive into the research topics of 'Exploring transistor width effect on stress-induced performance improvement in PMOSFET with SiGe source/drain'. Together they form a unique fingerprint.

Cite this