Failure factor based yield enhancement for SRAM designs

Yu Tsao Hsing, Chih Wea Wang, Ching Wei Wu, Chih Tsun Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

With the increasing chip density, semiconductor memory yield improvement is becoming a task that can only be done collaboratively by test engineers, product engineers, process engineers, and circuit designers. Design-for-manufacturability (DFM) and design-for-yield (DFY) methodologies have an increasing impact on the yield learning of modern silicon chips. However, a majority part of a system chip is typically occupied by memories, which dominate the yield of the chip. During chip integration, it is important that we pick the right design of memory cores that will maximize the yield under the specific process technology chosen. Traditionally, yield prediction is only based on layout and defect statistics. In this paper, we propose to estimate the yield with failure factor. We thus develop a memory failure factor analyzer (FFA), based on that we can select the memory design that is more suitable for the given process technology. Experimental results show that we can efficiently evaluate the yields of different memory designs for the same specification, so that the most robust one that results in the highest yield can be selected.

Original languageEnglish
Title of host publicationProceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
EditorsR. Aitken, A. Salsano, R. Velazco, X. Sun
Pages20-28
Number of pages9
DOIs
Publication statusPublished - 2004 Dec 1
Event19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Cannes, France
Duration: 2004 Oct 102004 Oct 13

Publication series

NameIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Conference

Conference19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
CountryFrance
CityCannes
Period04-10-1004-10-13

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Fingerprint Dive into the research topics of 'Failure factor based yield enhancement for SRAM designs'. Together they form a unique fingerprint.

  • Cite this

    Hsing, Y. T., Wang, C. W., Wu, C. W., Huang, C. T., & Wu, C. W. (2004). Failure factor based yield enhancement for SRAM designs. In R. Aitken, A. Salsano, R. Velazco, & X. Sun (Eds.), Proceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp. 20-28). (IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFTVS.2004.1347821