Fast and memory-efficient diagnostic fault simulation for sequential circuits

Jer Min Jou, Shung Chih Chen

Research output: Contribution to journalConference articlepeer-review

3 Citations (Scopus)

Abstract

In this paper, a fast and memory-efficient diagnostic fault simulator for sequential circuits is proposed. In it, a two-level optimization technique is developed and used to prompt the processing speed. In the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining algorithm are applied, thus the number of diagnostic comparisons is minimized. In the second low level, a bit-parallel comparison is developed to speed up the comparing process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simulator is extended to diagnose the single stuck-at device fault. Experimental results show that this diagnostic simulator achieves a significant speedup compared to previous methods.

Original languageEnglish
Pages (from-to)723-726
Number of pages4
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication statusPublished - 1994 Dec 1
EventProceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: 1994 Nov 61994 Nov 10

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Fast and memory-efficient diagnostic fault simulation for sequential circuits'. Together they form a unique fingerprint.

Cite this