Dynamic reconfigurable FPGAs provide a platform for reconfigurable computing as well as fast prototyping and emulation. For such FPGAs, we propose a dynamic serial (DS) test approach which takes advantage of their dynamic reconfiguration feature for testing. Compared with the parallel approach, the DS test approach significantly reduces the test configuration time and requires less I/O pins, resulting in faster and easier testing procedure for dynamic reconfigurable FPGAs.
|Number of pages||4|
|Journal||International Symposium on VLSI Technology, Systems, and Applications, Proceedings|
|Publication status||Published - 1999 Jan 1|
|Event||Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan|
Duration: 1999 Jun 7 → 1999 Jun 10
All Science Journal Classification (ASJC) codes