Fault detection and location of dynamic reconfigurable FPGAs

Chi Feng Wu, Cheng Wen Wu

Research output: Contribution to journalConference article

9 Citations (Scopus)

Abstract

Dynamic reconfigurable FPGAs provide a platform for reconfigurable computing as well as fast prototyping and emulation. For such FPGAs, we propose a dynamic serial (DS) test approach which takes advantage of their dynamic reconfiguration feature for testing. Compared with the parallel approach, the DS test approach significantly reduces the test configuration time and requires less I/O pins, resulting in faster and easier testing procedure for dynamic reconfigurable FPGAs.

Original languageEnglish
Pages (from-to)215-218
Number of pages4
JournalInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
Publication statusPublished - 1999 Jan 1
EventProceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan
Duration: 1999 Jun 71999 Jun 10

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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