Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM

Cheng-Wen Wu, K.-W. Hou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationVLSI Test Technology Workshop (VTTW)
Place of PublicationNantou
Publication statusPublished - 2017 Jul

Cite this

Wu, C-W., & Hou, K-W. (2017). Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM. In VLSI Test Technology Workshop (VTTW)