Abstract
Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experiences of the FA engineer is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new development flow that enables the product to reach a profitable yield level as soon as possible. Demand in methodologies that allow FA automation thus increases rapidly in recent years. This paper proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit-level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main contribution of the paper is thus a methodology and procedure for accelerating FA and yield optimization for semiconductor memories.
Original language | English |
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Pages (from-to) | 29-38 |
Number of pages | 10 |
Journal | IEEE International Test Conference (TC) |
Publication status | Published - 2003 |
Event | Proceedings International Test Conference 2003 - Charlotte, NC, United States Duration: 2003 Sep 30 → 2003 Oct 2 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Applied Mathematics