Fault simulation and test algorithm generation for random access memories

Chi Feng Wu; Chih Tsun Huang; Kuo Liang Cheng; Cheng Wen Wu

doi:10.1109/43.992771

Fault simulation and test algorithm generation for random access memories

Chi Feng Wu, Chih Tsun Huang, Kuo Liang Cheng, Cheng Wen Wu

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

37 Citations (Scopus)

Abstract

The size and density of semiconductor memories is rapidly growing, making them increasingly harder to test. New fault models and test algorithms have been continuously proposed to cover defects and failures of modern memory chips and cores. However, software tool support for automating the memory test development procedure is still insufficient. For this purpose, we have developed a fault simulator (called RAMSES) and a test algorithm generator (called TAGS) for random-access memories (RAMs). In this paper, we present the algorithms and other details of RAMSES and TAGS and the experimental results of these tools on various memory architectures and configurations. We show that efficient test algorithms can be generated automatically for bit-oriented memories, word-oriented memories, and multiport memories, with 100% coverage of the given typical RAM faults.

Original language	English
Pages (from-to)	480-490
Number of pages	11
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	21
Issue number	4
DOIs	https://doi.org/10.1109/43.992771
Publication status	Published - 2002 Apr 1

All Science Journal Classification (ASJC) codes

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/43.992771

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Fault simulation and test algorithm generation for random access memories

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